Implementation of Present Cryptographical Algorithm for the Encryption of Messages in NETFPGA 1G
01 Dec 2015-pp 1115-1119
TL;DR: A lightweight cryptographic algorithm called Present algorithm is used to enhance the security in netfpga by creating a module dedicated for encrypting the data transmitted by the netFPGA.
Abstract: The NetFPGA is a low-cost reconfigurable hardware platform optimized for high-speed networking. The NetFPGA includes all the logic resources, memory, and Gigabit Ethernet interfaces required to build a complete switch, router, and/or any other security device. Because the entire data path is implemented in hardware, the system can support back-to-back packets at full Gigabit line rates and has a processing latency measured in very few clock cycles. The security of the packet transfer using NETFPGA is one that has not yet been implemented on a more secure scale due to hardware limitation as many of the advanced algorithms such as AES or DES cannot be used due to their high complexity and excessive use of resources. In light of this I used a lightweight cryptographic algorithm called Present algorithm to enhance the security in netfpga by creating a module dedicated for encrypting the data transmitted by the netfpga. The algorithm is implemented using Xilinx for the initial testing and then the bit file is burned on the chip for real time emulation. Once the ping or rather the connection between the two connected machines is established the encrypted message is sent from the transmitter to the receiver and the output is observed.
Citations
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01 Jun 2018
TL;DR: A new hardware architecture design has been developed here for both PRESENT and HIGHT, and a significant design optimization has been achieved for HIGHT and asignificant throughput has be achieved for PRESENT.
Abstract: Light weight cryptography is a technology for providing the security solutions for the hardware systems where there is no computational resource or limited resource. PRESENT and HIGHT are a class of lightweight block ciphers which uses two different ways of computational structure for cipher generation. The paper presents the design and FPGA implementation of the two cryptographic structures PRESENT and HIGHT. A new hardware architecture design has been developed here for both PRESENT and HIGHT. A comparative analysis of the presented designs PRESENT and HIGHT have been done with the existing designs. A significant design optimization has been achieved for HIGHT and a significant throughput has been achieved for PRESENT.
5 citations
Cites methods from "Implementation of Present Cryptogra..."
...To provide a secure packet transmission on NetFPGA Chouhan [13], has proposed a convenient cryptographic algorithm which is known as Present algorithm....
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TL;DR: This work has emulated the hardware implementation of BBALR and compared its performance with the outputs of other prominent energy-saving policies based on dynamic link rate adaption, and mapped the energy savings from the measured sleep time and reference power values.
Abstract: In recent times, energy consumption in communication media has been increasing drastically. In the literature, energy-saving techniques that enable network devices to enter sleep state or limit the data rate have been proposed to reduce energy costs. In our earlier work, we proposed an energy-saving technique called burst-based adaptive link rate BBALR , the simulation of which assures increased energy savings. In this paper, we have emulated the hardware implementation of BBALR and compared its performance with the outputs of other prominent energy-saving policies based on dynamic link rate adaption. The energy savings are mapped from the measured sleep time and reference power values. We have used NetFPGA as the testbed, which is a research platform for building real-time network hardware prototypes.
2 citations
TL;DR: In this article , a 48-bit and 96-bit pipelined architectures of PRINT Ciphers are implemented on different field programmable gate array and application-specific integrated circuit platforms.
Abstract: With the enhancement of technology, data security has become incredibly significant. Nowadays, images and vital information are used in real-time, and high throughput architecture is required for internet of things and real-time applications. We mainly focus on the high throughput architecture of PRINT cipher. PRINT cipher is a lightweight block cipher with a block size of 48-bit and 96-bit. Loop-unrolled, 48-bit pipelined, and 96-bit pipelined architectures are designed and implemented on different field programmable gate array and application-specific integrated circuit platforms. The maximum operating frequency obtained for 48-bit pipelined is 259.67 MHz on Virtex-4 and 310.67 MHz for 96-bit pipelined on Virtex-5. Finally, with the help of a controller, 48-bit high throughput pipelined architecture was utilized for image encryption of both grayscale and color images. The security analysis of encrypted images for color and grayscale images using PRINT cipher shows better performance and more robust protection against statistical, entropy, and differential attacks.
30 Oct 2020
TL;DR: In this article, two PRESENT architectures are proposed in order to provide stronger security, with elevated performance and less power consumption, two architectures provide the option to choose one of the three MEC S-boxes, whereas the second architecture makes use of a single MECS-box to provide better security and increased performance for encryption and decryption processes.
Abstract: Cyber Physical Systems (CPS) is essential for the integration of the physical world with the virtual electronic world. The only way to provide security to these constrained environment applications is through Lightweight Cryptography. To provide stronger security, with elevated performance and less power consumption, two PRESENT architectures are proposed in this paper. The first architecture provides the option to choose one of the three MEC S-boxes, whereas the second architecture makes use of a single MEC S-box to provide better security and increased performance for encryption and decryption processes. The Standard S-box is replaced with MEC S-box, which has its own advantages, such as, less power consumption, linear time and constant space complexity. To analyse the various parameters of the proposed architectures, they are synthesized using Xilinx Virtex-7 FPGA, in Xilinx Vivado IDE. With respect to Strict Avalanche Criterion (SAC), the standard usage of S-box, nearly gives 50% SAC whereas, at least two orders of MEC S-boxes used in the proposed architectures give more than 50% SAC for the entire algorithm, thereby increasing the security of the whole process. The results depict that the proposed architecture provides a throughput of 1564.02 Mbps whereas with a lesser power consumption.
DOI•
TL;DR: In this article , the security analysis of encrypted images for color and grayscale images using PRINT cipher shows better performance and more robust protection against statistical, entropy, and differential attacks.
Abstract: Abstract. With the enhancement of technology, data security has become incredibly significant. Nowadays, images and vital information are used in real-time, and high throughput architecture is required for internet of things and real-time applications. We mainly focus on the high throughput architecture of PRINT cipher. PRINT cipher is a lightweight block cipher with a block size of 48-bit and 96-bit. Loop-unrolled, 48-bit pipelined, and 96-bit pipelined architectures are designed and implemented on different field programmable gate array and application-specific integrated circuit platforms. The maximum operating frequency obtained for 48-bit pipelined is 259.67 MHz on Virtex-4 and 310.67 MHz for 96-bit pipelined on Virtex-5. Finally, with the help of a controller, 48-bit high throughput pipelined architecture was utilized for image encryption of both grayscale and color images. The security analysis of encrypted images for color and grayscale images using PRINT cipher shows better performance and more robust protection against statistical, entropy, and differential attacks.
References
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01 Jan 2002
TL;DR: This volume is the authoritative guide to the Rijndael algorithm and AES and professionals, researchers, and students active or interested in data encryption will find it a valuable source of information and reference.
Abstract: From the Publisher:
In October 2000, the US National Institute of Standards and Technology selected the block cipher Rijndael as the Advanced Encryption Standard (AES). AES is expected to gradually replace the present Data Encryption Standard (DES) as the most widely applied data encryption technology.|This book by the designers of the block cipher presents Rijndael from scratch. The underlying mathematics and the wide trail strategy as the basic design idea are explained in detail and the basics of differential and linear cryptanalysis are reworked. Subsequent chapters review all known attacks against the Rijndael structure and deal with implementation and optimization issues. Finally, other ciphers related to Rijndael are presented.|This volume is THE authoritative guide to the Rijndael algorithm and AES. Professionals, researchers, and students active or interested in data encryption will find it a valuable source of information and reference.
2,140 citations
TL;DR: It is shown that the key-scheduling algorithms of many blockciphers inherit obvious relationships between keys, and use these key relations to attack the blockcips, and that DES is not vulnerable to the related keys attacks.
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529 citations
14 Aug 2000
TL;DR: It is confirmed that Camellia provides strong security against differential and linear cryptanalyses and at least comparable encryption speed in software and hardware.
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403 citations
01 Jan 2000
TL;DR: Camellia as discussed by the authors is a new 128-bit block cipher with 128-, 192-, and 256-bit key lengths, which was designed to withstand all known cryptanalytic attacks and even to have a sufficiently large security leeway for use of the next 10-20 years.
Abstract: We present a new 128-bit block cipher called Camellia. Camellia sup- ports 128-bit block size and 128-, 192-, and 256-bit key lengths, i.e. the same interface specifications as the Advanced Encryption Standard (AES). Camellia was carefully designed to withstand all known cryptanalytic attacks and even to have a sufficiently large security leeway for use of the next 10-20 years. There are no hidden weakness inserted by the designers. It was also designed to have suitability for both software and hardware implementations and to cover all possible encryption applications that range from low-cost smart cards to high-speed network systems. Compared to the AES finalists, Camellia offers at least comparable encryption speed in software and hardware. An optimized implementation of Camellia in assembly language can en- crypt on a PentiumIII (800MHz) at the rate of m ore than 276 Mbits per second, which is much faster than the speed of an optimized DES implementation. In ad- dition, a distinguishing feature is its small hardware design. The hardware design, which includes key schedule, encryption and decryption, occupies approximately 11K gates, which is the smallest among all existing 128-bit block ciphers as far as we know. It perfectly meet current market requirements in wireless cards, for instance, where low power consumption is a mandaroty condition.
377 citations
23 Mar 1998
TL;DR: In this paper, the DES S-boxes are used in a new structure that simultaneously allows a more rapid avalanche, a more efficient bitslice implementation, and an easy analysis that enables them to demonstrate its security against all known types of attack.
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255 citations