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Proceedings ArticleDOI: 10.1109/CICN.2015.219

Implementation of Present Cryptographical Algorithm for the Encryption of Messages in NETFPGA 1G

01 Dec 2015-pp 1115-1119
Abstract: The NetFPGA is a low-cost reconfigurable hardware platform optimized for high-speed networking. The NetFPGA includes all the logic resources, memory, and Gigabit Ethernet interfaces required to build a complete switch, router, and/or any other security device. Because the entire data path is implemented in hardware, the system can support back-to-back packets at full Gigabit line rates and has a processing latency measured in very few clock cycles. The security of the packet transfer using NETFPGA is one that has not yet been implemented on a more secure scale due to hardware limitation as many of the advanced algorithms such as AES or DES cannot be used due to their high complexity and excessive use of resources. In light of this I used a lightweight cryptographic algorithm called Present algorithm to enhance the security in netfpga by creating a module dedicated for encrypting the data transmitted by the netfpga. The algorithm is implemented using Xilinx for the initial testing and then the bit file is burned on the chip for real time emulation. Once the ping or rather the connection between the two connected machines is established the encrypted message is sent from the transmitter to the receiver and the output is observed.

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Topics: NetFPGA (79%), Gigabit Ethernet (54%), Gigabit (54%) ...read more
Citations
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Proceedings ArticleDOI: 10.1109/ICCONS.2018.8663165
R.S. Mahantesh1, Sasmita Mohapatra1Institutions (1)
01 Jun 2018-
Abstract: Light weight cryptography is a technology for providing the security solutions for the hardware systems where there is no computational resource or limited resource. PRESENT and HIGHT are a class of lightweight block ciphers which uses two different ways of computational structure for cipher generation. The paper presents the design and FPGA implementation of the two cryptographic structures PRESENT and HIGHT. A new hardware architecture design has been developed here for both PRESENT and HIGHT. A comparative analysis of the presented designs PRESENT and HIGHT have been done with the existing designs. A significant design optimization has been achieved for HIGHT and a significant throughput has been achieved for PRESENT.

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Topics: Cipher (54%), Hardware architecture (52%), Cryptography (51%) ...read more

3 Citations


Open accessJournal ArticleDOI: 10.3906/ELK-1906-180
Abstract: In recent times, energy consumption in communication media has been increasing drastically. In the literature, energy-saving techniques that enable network devices to enter sleep state or limit the data rate have been proposed to reduce energy costs. In our earlier work, we proposed an energy-saving technique called burst-based adaptive link rate BBALR , the simulation of which assures increased energy savings. In this paper, we have emulated the hardware implementation of BBALR and compared its performance with the outputs of other prominent energy-saving policies based on dynamic link rate adaption. The energy savings are mapped from the measured sleep time and reference power values. We have used NetFPGA as the testbed, which is a research platform for building real-time network hardware prototypes.

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  • Figure 3. State diagram of the system.
    Figure 3. State diagram of the system.
  • Figure 4. NetFPGA 1G CML architecture.
    Figure 4. NetFPGA 1G CML architecture.
  • Figure 8. Comparison of waiting time in milliseconds for different traffic rates.
    Figure 8. Comparison of waiting time in milliseconds for different traffic rates.
  • Figure 9. Comparison of sleeping time in milliseconds for different traffic rates.
    Figure 9. Comparison of sleeping time in milliseconds for different traffic rates.
  • Figure 13. Projected power consumption in watt-hours per day (a) and stipulated energy savings in percentage (b).
    Figure 13. Projected power consumption in watt-hours per day (a) and stipulated energy savings in percentage (b).
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Topics: NetFPGA (67%), Energy consumption (56%), Networking hardware (55%) ...read more

2 Citations


Proceedings ArticleDOI: 10.1109/DISCOVER50404.2020.9278038
30 Oct 2020-
Abstract: Cyber Physical Systems (CPS) is essential for the integration of the physical world with the virtual electronic world. The only way to provide security to these constrained environment applications is through Lightweight Cryptography. To provide stronger security, with elevated performance and less power consumption, two PRESENT architectures are proposed in this paper. The first architecture provides the option to choose one of the three MEC S-boxes, whereas the second architecture makes use of a single MEC S-box to provide better security and increased performance for encryption and decryption processes. The Standard S-box is replaced with MEC S-box, which has its own advantages, such as, less power consumption, linear time and constant space complexity. To analyse the various parameters of the proposed architectures, they are synthesized using Xilinx Virtex-7 FPGA, in Xilinx Vivado IDE. With respect to Strict Avalanche Criterion (SAC), the standard usage of S-box, nearly gives 50% SAC whereas, at least two orders of MEC S-boxes used in the proposed architectures give more than 50% SAC for the entire algorithm, thereby increasing the security of the whole process. The results depict that the proposed architecture provides a throughput of 1564.02 Mbps whereas with a lesser power consumption.

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Topics: Encryption (52%), Throughput (business) (51%)
References
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01 Jan 2002-
Abstract: From the Publisher: In October 2000, the US National Institute of Standards and Technology selected the block cipher Rijndael as the Advanced Encryption Standard (AES). AES is expected to gradually replace the present Data Encryption Standard (DES) as the most widely applied data encryption technology.|This book by the designers of the block cipher presents Rijndael from scratch. The underlying mathematics and the wide trail strategy as the basic design idea are explained in detail and the basics of differential and linear cryptanalysis are reworked. Subsequent chapters review all known attacks against the Rijndael structure and deal with implementation and optimization issues. Finally, other ciphers related to Rijndael are presented.|This volume is THE authoritative guide to the Rijndael algorithm and AES. Professionals, researchers, and students active or interested in data encryption will find it a valuable source of information and reference.

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1,974 Citations


Journal ArticleDOI: 10.1007/BF00203965
Eli Biham1Institutions (1)
Abstract: In this paper we study the influence of key-scheduling algorithms on the strength of blockciphers. We show that the key-scheduling algorithms of many blockciphers inherit obvious relationships between keys, and use these key relations to attack the blockciphers. Two new types of attacks are described: New chosen plaintext reductions of the complexity of exhaustive search attacks (and the faster variants based on complementation properties), and new low-complexity chosen key attacks. These attacks are independent of the number of rounds of the cryptosystems and of the details of the F-function and may have very small complexities. These attacks show that the key-scheduling algorithm should be carefully designed and that its structure should not be too simple. These attacks are applicable to both variants of LOKI and to Lucifer. DES is not vulnerable to the related keys attacks since the shift pattern in the key-scheduling algorithm is not the same in all the rounds.

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Topics: Related-key attack (59%), Slide attack (52%), Plaintext (51%)

498 Citations


Open access
01 Jan 2000-
Abstract: We present a new 128-bit block cipher called Camellia. Camellia sup- ports 128-bit block size and 128-, 192-, and 256-bit key lengths, i.e. the same interface specifications as the Advanced Encryption Standard (AES). Camellia was carefully designed to withstand all known cryptanalytic attacks and even to have a sufficiently large security leeway for use of the next 10-20 years. There are no hidden weakness inserted by the designers. It was also designed to have suitability for both software and hardware implementations and to cover all possible encryption applications that range from low-cost smart cards to high-speed network systems. Compared to the AES finalists, Camellia offers at least comparable encryption speed in software and hardware. An optimized implementation of Camellia in assembly language can en- crypt on a PentiumIII (800MHz) at the rate of m ore than 276 Mbits per second, which is much faster than the speed of an optimized DES implementation. In ad- dition, a distinguishing feature is its small hardware design. The hardware design, which includes key schedule, encryption and decryption, occupies approximately 11K gates, which is the smallest among all existing 128-bit block ciphers as far as we know. It perfectly meet current market requirements in wireless cards, for instance, where low power consumption is a mandaroty condition.

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Topics: Triple DES (62%), 40-bit encryption (61%), Disk encryption hardware (60%) ...read more

377 Citations


Open accessBook ChapterDOI: 10.1007/3-540-44983-3_4
Kazumaro Aoki1, Tetsuya Ichikawa2, Masayuki Kanda1, Mitsuru Matsui2  +3 moreInstitutions (2)
14 Aug 2000-
Abstract: We present a new 128-bit block cipher called Camellia. Camellia supports 128-bit block size and 128-, 192-, and 256-bit keys, i.e., the same interface specifications as the Advanced Encryption Standard (AES). Efficiency on both software and hardware platforms is a remarkable characteristic of Camellia in addition to its high level of security. It is confirmed that Camellia provides strong security against differential and linear cryptanalyses. Compared to the AES finalists, i.e., MARS, RC6, Rijndael, Serpent, and Twofish, Camellia offers at least comparable encryption speed in software and hardware. An optimized implementation of Camellia in assembly language can encrypt on a Pentium III (800MHz) at the rate of more than 276 Mbits per second, which is much faster than the speed of an optimized DES implementation. In addition, a distinguishing feature is its small hardware design. The hardware design, which includes encryption and decryption and key schedule, occupies approximately 11K gates, which is the smallest among all existing 128-bit block ciphers as far as we know.

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Topics: Advanced Encryption Standard process (61%), Twofish (61%), Advanced Encryption Standard (60%) ...read more

358 Citations


Open accessBook ChapterDOI: 10.1007/3-540-69710-1_15
Eli Biham1, Ross Anderson2, Lars R. Knudsen3Institutions (3)
23 Mar 1998-
Abstract: We propose a new block cipher as a candidate for the Advanced Encryption Standard. Its design is highly conservative, yet still allows a very efficient implementation. It uses the well-understood DES S-boxes in a new structure that simultaneously allows a more rapid avalanche, a more efficient bitslice implementation, and an easy analysis that enables us to demonstrate its security against all known types of attack. With a 128-bit block size and a 256-bit key, it is almost as fast as DES on a wide range of platforms, yet conjectured to be at least as secure as three-key triple-DES.

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Topics: Triple DES (66%), CBC-MAC (65%), Block cipher (62%) ...read more

230 Citations


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