Implementation of the Density Gradient Quantum Corrections for 3-D Simulations of Multigate Nanoscaled Transistors
01 Jun 2011-IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE)-Vol. 30, Iss: 6, pp 841-851
TL;DR: Test simulations of a 1-D metal-oxide semiconductor diode demonstrate that the DG approach discretized using the new, second-order differential (SOD) scheme can be accurately calibrated against Schrödinger-Poisson calculations exhibiting lower discretization error than the previous schemes when using coarse grids.
Abstract: An efficient implementation of the density-gradient (DG) approach for the finite element and finite difference methods and its application in drift-diffusion (D-D) simulations is described in detail. The new, second-order differential (SOD) scheme is compatible with relatively coarse grids even for large density variations thus applicable to device simulations with complex 3-D geometries. Test simulations of a 1-D metal-oxide semiconductor diode demonstrate that the DG approach discretized using our SOD scheme can be accurately calibrated against Schrodinger-Poisson calculations exhibiting lower discretization error than the previous schemes when using coarse grids and the same results for very fine meshes. 3-D test D-D simulations using the finite element method are performed on two devices: a 10 nm gate length double gate metal-oxide-semiconductor field-effect transistor (MOSFET) and a 40 nm gate length Tri-Gate fin field-effect transistor (FinFET). In 3-D D-D simulations, the SOD scheme is able to converge to physical solutions at high voltages even if the previous schemes fail when using the same mesh and equivalent conditions. The quantum corrected D-D simulations using the SOD scheme also converge with an atomistic mesh used for the 10 nm double gate MOSFET saving computational resources and can be accurately calibrated against the results from non-equilibrium Green's functions approach. Finally, the simulated ID-VG characteristics for the 40 nm gate length Tri-Gate are in an excellent agreement with experimental data.
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TL;DR: In this article, the performance, scalability, and resilience of Si SOI FinFETs and gate-all-around (GAA) nanowires (NWs) are studied using in-house-built 3D simulation tools.
Abstract: Performance, scalability, and resilience to variability of Si SOI FinFETs and gate-all-around (GAA) nanowires (NWs) are studied using in-house-built 3-D simulation tools. Two experimentally based devices, a 25-nm gate length FinFET and a 22-nm GAA NW are modeled and then scaled down to 10.7- and 10-nm gate lengths, respectively. A TiN metal gate work-function granularity (MGG) and line edge roughness (LER) induced variability affecting OFF and ON characteristics are investigated and compared. In the OFF-region, the FinFETs have over an order of magnitude larger OFF-current that those of the equivalent GAA NWs. In the ON-region, the 25/10.7-nm gate length FinFETs deliver 20/58% larger ON-current than the 22/10-nm gate length GAA NWs. The FinFETs are more resilient to the MGG and LER variability in the subthreshold compared to the GAA NWs. However, the MGG ON-current variability is larger for the 10.7-nm FinFET than that for the 10-nm GAA NW. The LER ON-current variability depends largely on the RMS height; whereas a 0.6-nm RMS height yields a similar variability for both FinFETs and GAA NWs. Finally, the industry preferred 〈110〉 channel orientation is more resilient to the MGG and LER variability in both architectures.
140 citations
Cites methods from "Implementation of the Density Gradi..."
...Consequently, a density-gradient (DG) approach is used with the DD simulations [30]....
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TL;DR: Nanosheet (NS) and nanowire FET architectures scaled to a gate length of 16 nm and below are benchmarked against equivalent FinFETs and the NW FET becomes the most promising architecture offering an almost ideal sub-threshold swing.
Abstract: Nanosheet (NS) and nanowire (NW) FET architectures scaled to a gate length ( $L_{\textbf {G}}$ ) of 16 nm and below are benchmarked against equivalent FinFETs. The device performance is predicted using a 3D finite element drift-diffusion/Monte Carlo simulation toolbox with integrated 2D Schrodinger equation based quantum corrections. The NS FET is a viable replacement for the FinFET in high performance (HP) applications when scaled down to $L_{\textbf {G}}$ of 16 nm offering a larger on-current ( $I_{\textbf {ON}}$ ) and slightly better sub-threshold characteristics. Below $\text{L}_{\textbf {G}}$ of 16 nm, the NW FET becomes the most promising architecture offering an almost ideal sub-threshold swing, the smallest off-current ( $I_{\textbf {OFF}}$ ), and the largest $I_{\textbf {ON}}/I_{\textbf {OFF}}$ ratio out of the three architectures. However, the NW FET suffers from early $I_{\textrm {ON}}$ saturation with the increasing gate bias that can be tackled by minimizing interface roughness and/or by optimisation of a doping profile in the device body.
54 citations
Additional excerpts
...VENDES is a 3D FE physically-based simulation toolbox for nanoscaled devices [17], [24], [25] that integrates a 2D Schrödinger equation (SCH) based quantum corrected 3D...
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TL;DR: A 3-D quantum-corrected drift-diffusion (DD) simulation study of three sources of statistical variability, including discrete random dopants, line-edge roughness (LER), and metal gate workfunction (MGW) was performed for a 14-nm gate length FinFET in the subthreshold region using Fermi-Dirac statistics.
Abstract: A 3-D quantum-corrected drift-diffusion (DD) simulation study of three sources of statistical variability, including discrete random dopants (RDs), line-edge roughness (LER), and metal gate workfunction (MGW) was performed for a 14-nm gate length In0.53Ga0.47As FinFET in the subthreshold region using Fermi-Dirac statistics. This paper has been done at both low (0.05 V) and high drain biases (0.6 V). The LER variability is characterized by the root mean square amplitude (Δ) and correlation length (Λ), and the MGW variability by the metal grain size (GS). The RD-induced variation σ VT = 6 mV is similar to that observed in Si SoI FinFETs. The LER-induced threshold voltage variations (σ VT <; 6 mV) are similar to the RD variations when Δ = 1 nm, and smaller than the observed in Si SoI FinFETs (18 mV). For larger A, the LER exhibits σ VT ranging from 11 mV when Λ = 10 nm and Δ = 2 nm to 19 mV when Λ = 20 nm and Δ = 3 nm. The MGW variations are the dominant source of variability in the subthreshold characteristics, the σ VT ranges from 106 mV when GS = 10 nm to 43 mV when GS = 3 nm, which is larger than those observed in equivalent TiN metal-gate Si FinFETs.
44 citations
TL;DR: A 3D ensemble Monte Carlo simulation tool with quantum corrections based on the tetrahedral decomposition of a simulation domain has been developed for the modeling of electron transport in nonplanar nano-MOSFETs as mentioned in this paper.
Abstract: A 3D ensemble Monte Carlo device simulation tool with quantum corrections based on the tetrahedral decomposition of a simulation domain has been developed for the modeling of electron transport in nonplanar nano-MOSFETs. This 3D tool includes a presimulation drift-diffusion transport model which can also be used separately. A discretization by finite element method can accurately describe a 3D device geometry and speed up complex 3D simulations. The quantum corrections are included via a density gradient approach and the interface roughness via Ando's model. ID - VG characteristics of a 25-nm gate length Si silicon-on-insulator (SOI) FinFET, selected as an application example, shows an excellent agreement with experimental data including the subthreshold slope. We show that the device on-current for a (110) channel orientation could be improved by about 15% for a (100) channel orientation. The role of quantization of energy levels affecting the distribution of electron density at sidewalls of the SOI FinFET is found to be different at low (0.05 V) and high (1.0 V) gate biases.
41 citations
Cites background or methods from "Implementation of the Density Gradi..."
...Our implementation of the DG approach allows the change of the quantization masses with the orientation [10], using them as calibration parameters against quantum mechanical models....
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...An efficient 3D FE ensemble MC device simulation code with quantum corrections [10] was developed for physical modeling of nonplanar semiconductor transistors such as FinFETs and nanowire FETs....
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...The quantum mechanical confinement effects are included using the DG equation for electrons [10]....
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...In this paper, we have included the DG approach [10], [13] as a...
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...In addition, the effects due to quantum confinement must also be taken into account because the device dimensions are within deep sub-100 nm [10], [12]....
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TL;DR: In this article, the 2-D Schrodinger equation is solved at prescribed transverse planes of the 3-D mesh in the transport direction, and the results are then compared with those obtained from 3D FE MC simulations with quantum corrections via the density gradient method showing very similar I-V characteristics but very different density distributions.
Abstract: Solutions of the 2-D Schrodinger equation across the channel using a finite element method have been implemented into a 3-D finite element (FE) ensemble Monte Carlo (MC) device simulation toolbox as quantum corrections. The 2-D FE Schrodinger equation-based quantum corrections are entirely calibration free and can accurately describe quantum confinement effects in arbitrary device cross sections. The 3-D FE quantum corrected MC simulation is based on the tetrahedral decomposition of the simulation domain and the 2-D Schrodinger equation is solved at prescribed transverse planes of the 3-D mesh in the transport direction. We apply the method to study output characteristics of a nonplanar nanoscaled MOSFET, a{10.7}-nm gate length silicon-on-insulator FinFET, investigating 〈100〉 and 〈110〉 channel orientations. The results are then compared with those obtained from 3-D FE MC simulations with quantum corrections via the density gradient method showing very similar I-V characteristics but very different density distributions.
37 citations
Cites methods from "Implementation of the Density Gradi..."
...The combination of the FEM with an ensemble Monte Carlo (MC) technique [8], which is well recognized as a semiclassical transport model with an accurate predictive power, is equally challenging due to the unstructured mesh [9]....
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...D FE MC simulation toolbox [6] has included quantum corrections using the density gradient (DG) approach adapted for the FEM [15]....
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...The 3-D MC toolbox, based on tetrahedral elements, solves the Poisson equation and performs the real-space classical movement of particles and their quantum-mechanical scatterings in k-space [6], [15]....
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...In [6], the quantum corrections are based on the DG approach [15] and they are assumed to be fixed during an MC simulation (the frozen quantum potential approach [27])....
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...The 3-D FE MC simulation toolbox [6] has included quantum corrections using the density gradient (DG) approach adapted for the FEM [15]....
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TL;DR: In this article, the experimental dependence of carrier mobilities on doping density and field strength in silicon has been investigated and the curve-fitting procedures are described, which fit the experimental data.
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01 Jan 1997
TL;DR: Metis is copyrighted by the regents of the University of Minnesota as mentioned in this paper, and the content of which does not necessarily reflect the position or the policy of lhe government, and no official endorsement should be inferred.
Abstract: Metis is copyrighted by the regents of the University of Minnesota. This work was supponed by IST/BMDO through Army Research Office
contract DA/DAAH04-93-G-0080. and by Army High Performance Computing Research Center under the auspices of the Department of the Army.
Anny Research Laboratory cooperative agreement number DAAH04-95-2-0003/contract number DAAH04-95-C-0008, the content of which does
not necessarily reflect the position or the policy of lhe government, and no official endorsement should be inferred. Access to computing facilities
were provided by Minnesota Supercomputer Institute, Cray Research Inc, and by the Pittsburgh Supercomputing Center.
1,018 citations
TL;DR: In this paper, the authors describe the evolution and properties of a new class of MOSFETs, called triple-plus (3 + )-gate devices, which offer a practical solution to the problem of the ultimate, yet manufacturable, silicon MOS-FET.
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878 citations