Implementing fast Fourier transforms using the Am29500 family
TL;DR: The implementation of fast Fourier transform (FFT) algorithms using members of the Am29500 family of microprocessors and peripherals is discussed, mainly on radix-2 decimation-in-time (DIT) FFT computations, but the architecture described can be applied to variable-radix processors running DIT or DIF algorithms.
About: This article is published in Microprocessors and Microsystems.The article was published on 1987-10-01. It has received 1 citations till now. The article focuses on the topics: Prime-factor FFT algorithm & Fast Fourier transform.
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TL;DR: Digital systems composed of a number of cooperating microprogrammed units are considered and a Patri-net-based modeling method of C-MIDDLE programs as well as a verification system VECOM built around this method are presented.
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TL;DR: Good generalized these methods and gave elegant algorithms for which one class of applications is the calculation of Fourier series, applicable to certain problems in which one must multiply an N-vector by an N X N matrix which can be factored into m sparse matrices.
Abstract: An efficient method for the calculation of the interactions of a 2' factorial ex- periment was introduced by Yates and is widely known by his name. The generaliza- tion to 3' was given by Box et al. (1). Good (2) generalized these methods and gave elegant algorithms for which one class of applications is the calculation of Fourier series. In their full generality, Good's methods are applicable to certain problems in which one must multiply an N-vector by an N X N matrix which can be factored into m sparse matrices, where m is proportional to log N. This results inma procedure requiring a number of operations proportional to N log N rather than N2. These methods are applied here to the calculation of complex Fourier series. They are useful in situations where the number of data points is, or can be chosen to be, a highly composite number. The algorithm is here derived and presented in a rather different form. Attention is given to the choice of N. It is also shown how special advantage can be obtained in the use of a binary computer with N = 2' and how the entire calculation can be performed within the array of N data storage locations used for the given Fourier coefficients. Consider the problem of calculating the complex Fourier series N-1 (1) X(j) = EA(k)-Wjk, j = 0 1, * ,N- 1, k=0
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TL;DR: The problems associated with implementing the FFT algorithm in hardware and many of the design options applicable to an FFT processor are described, and a brief comparison of several machine organizations is given.
Abstract: This discussion served as an introduction to the Hardware Implementations Session of the IEEE Workshop on Fast Fourier Transform Processing. It introduces the problems associated with implementing the FFT algorithm in hardware and provides a frame of reference for characterizing specific implementations. Many of the design options applicable to an FFT processor are described, and a brief comparison of several machine organizations is given.
64 citations