Improved method of cell placement with symmetry constraints for analog IC layout design
09 Apr 2006-Vol. 2006, pp 192-199
TL;DR: An efficient method to obtain the closest cell placement satisfying the given symmetry constraints and the topology constraints imposed by a sequence-pair using linear programming is proposed.
Abstract: Recently, it is often required in high performance analog IC design that some cells are placed symmetrically to horizontal or vertical axis. Balasa et al. proposed a method of obtaining the closest placement satisfying the given symmetry constraints and the topology constraints imposed by a sequence-pair, but this method has the following defects: (1) Some cells overlap each other. (2) The closest cell placement satisfying both the symmetry and topology constraints may not be obtained. (3) How to place cells symmetrically is mentioned only for one axis and there is no explanation for plural axes. In this paper, we propose an efficient method to obtain the closest cell placement satisfying the given symmetry constraints and the topology constraints imposed by a sequence-pair using linear programming. The proposed method obtains a simple constraint graph from a sequence-pair and derives a set of linear constraint expressions from the graph. The number of linear expressions decreases by substituting the expressions for dependent variables. Then the solutions are obtained by linear programming. The effectiveness of the proposed method was shown by computational experiments.
Citations
More filters
TL;DR: This is the first piece of work that can handle symmetry constraint, common centroid constraint, and other general placement constraints, simultaneously, simultaneously.
Abstract: In today's system-on-chip designs, both digital and analog parts of a circuit will be implemented on the same chip. Parasitic mismatch induced by layout will affect circuit performance significantly for analog designs. Consideration of symmetry and common centroid constraints during placement can help to reduce these errors. Besides these two specific types of placement constraints, other constraints, such as alignment, abutment, preplace, and maximum separation, are also essential in circuit placement. In this paper, we will present a placement methodology that can handle all these constraints at the same time. To the best of our knowledge, this is the first piece of work that can handle symmetry constraint, common centroid constraint, and other general placement constraints, simultaneously. Experimental results do confirm the effectiveness and scalability of our approach in solving this mixed constraint-driven placement problem.
77 citations
10 Nov 2008
TL;DR: The analog placement algorithm Plantage generates placements for analog circuits with comprehensive placement constraints, based on a hierarchically bounded enumeration of basic building blocks, using B*-trees, which is the Pareto front of placements with respect to different aspect ratios.
Abstract: The analog placement algorithm Plantage, presented in this paper, generates placements for analog circuits with comprehensive placement constraints. Plantage is based on a hierarchically bounded enumeration of basic building blocks, using B*-trees. The practically relevant solution space is thereby enumerated quasi-complete. The sets of possible placements of the basic building blocks are represented and combined in a new efficient way, using enhanced shape functions. The result of Plantage is the Pareto front of placements with respect to different aspect ratios. The whole approach is deterministic, in contrast to existing analog placement algorithms.
68 citations
Cites background or methods from "Improved method of cell placement w..."
...Area SP [18] ST [16] SP+LP [29] SPwD [22] SymIs [21] SP+JPQ [20] This work Modules Sym....
[...]
...For that reason, placements were generated using Plantage for the circuits “biasynth 2p4g” and “lnamixbias 2p4g” used in [18], [16], [29], [22], [21], and [20]....
[...]
05 Nov 2006
TL;DR: This paper addresses this device-level placement problem for analog circuits and their approach can handle symmetry constraint and other placement constraints simultaneously, and results show that the approach can give solutions of better quality, in an acceptable amount of run time.
Abstract: In order to handle device matching in analog circuits, some pairs of modules are required to be placed symmetrically. This paper addresses this device-level placement problem for analog circuits and our approach can handle symmetry constraint and other placement constraints simultaneously. The problem of placing devices with symmetry constraint has been extensively studied but none of the previous works has considered symmetry constraint with other placement constraints simultaneously. Instead of handling the constraints by having a penalty term in the cost function to penalize violations, a unified method is proposed that, by adjusting the edge weights in a pair of constraint graphs, can try to satisfy all the placement and symmetry constraints simultaneously in a candidate floorplan solution. The maximum distance of the modules in a symmetry group from the corresponding symmetry axis will be minimized in this weight adjusting step, in order to minimize the total packing area. We have compared our method with the most updated results on this problem [2] when there are only symmetry constraints and results show that our approach can give solutions of better quality, in an acceptable amount of run time. We will also demonstrate the effectiveness of our approach in handling different types of constraints simultaneously by testing on data sets with both symmetry and other placement constraints, and the results are very promising.
59 citations
04 Jun 2007
TL;DR: This paper presents the first amortized linear-time packing algorithm for the placement with symmetry constraints and proposes automatically symmetric-feasible B*-trees (ASF-B*-Trees) to directly model the placement of a symmetry island.
Abstract: In this paper, we present the first amortized linear-time packing algorithm for the placement with symmetry constraints. We first introduce the concept of a symmetry island which is formed by modules of the same symmetry group in a single connected placement. Based on this concept and the B*-tree representation, we propose automatically symmetric-feasible B*-trees (ASF-B*-trees) to directly model the placement of a symmetry island. Unlike the previous works that can handle only ID symmetry constraints, our ASF-B*-tree is the first in the literature to additionally consider 2D symmetry. We then present hierarchical B*-trees (HB*-trees) which can simultaneously optimize the placement with both symmetry islands and non-symmetry modules. Unlike the previous works, our approach can guarantee the close proximity of symmetry modules and significantly reduce the search space based on the symmetry-island formulation. In particular, the packing time for an ASF-B*- tree or an HB*-tree is the same as that for a plain B*-tree (only amortized linear) and much faster than previous works which need at least loglinear time. Experimental results show that our approach achieves the best published quality and runtime efficiency for analog placement.
49 citations
19 Jan 2009
TL;DR: Significant improvements can be obtained by the approach in both common centroid and 1-D symmetry placements, and it is claimed that this work is the first who can handle both constraints simultaneously.
Abstract: In this paper, we will present a placement method for analog circuits. We consider both common centroid and 1-D symmetry constraints, which are the two most common types of placement requirements in analog designs. The approach is based on a symmetric feasible condition on the sequence pair representation that can cover completely the set of all placements satisfying the common centroid and 1-D symmetry constraints. This condition is essential for a good searching process to solve the problem effectively. Symmetric placement is an important step to achieve matchings of other electrical properties like delay and temperature variation. We have compared our results with those presented in the most updated previous works. Significant improvements can be obtained by our approach in both common centroid and 1-D symmetry placements, and we are the first who can handle both constraints simultaneously.
45 citations
Cites background from "Improved method of cell placement w..."
...However, these conditions are later found to be sufficient but not necessary [14]....
[...]
...[14] further looked into the symmetricfeasible condition in sequence pair and proposed a linear programming based method....
[...]
References
More filters
01 Dec 1995
TL;DR: A P-admissible solution space where each packing is represented by a pair of module name sequences is proposed, and hundreds of modules could be successfully packed as demonstrated.
Abstract: The first and the most critical stage in VLSI layout design is the placement, the background of which is the rectangle packing problem: Given many rectangular modules of arbitrary size, place them without overlapping on a layer in the smallest bounding rectangle. Since the variety of the packing is infinite (two- dimensionally continuous) many, the key issue for successful optimization is in the introduction of a P-admissible solution space, which is a finite set of solutions at least one of which is optimal. This paper proposes such a solution space where each packing is represented by a pair of module name sequences. Searching this space by simulated annealing, hundreds of modules could be successfully packed as demonstrated. Combining a conventional wiring method, the biggest MCNC benchmark ami49 is challenged.
391 citations
01 Jan 2000
TL;DR: This paper presents a new approach to evaluate a sequence pair based on comparing longest common subsequence in a pair of weighted sequences and presents a very simple and efficient O(n/sup 2/) algorithm to solve the sequence pair evaluation problem.
Abstract: Murata et al. (1996) introduced an elegant representation of block placement called sequence pair. All block placement algorithms which are based on sequence pairs use simulated annealing where the generation and evaluation of a large number of sequence pairs is required. Therefore, a fast algorithm is needed to evaluate each generated sequence pair, i.e. to translate the sequence pair to its corresponding block placement. This paper presents a new approach to evaluate a sequence pair based on comparing longest common subsequence in a pair of weighted sequences. We present a very simple and efficient O(n/sup 2/) algorithm to solve the sequence pair evaluation problem. We also show that using a more sophisticated data structure, the algorithm can be implemented to run in O(n log n) time. Both implementations of our algorithm are significantly faster than the previous O(n/sup 2/) graph-based algorithm. For example, we achieve 60/spl times/ speedup over the previous algorithm when input size n=128.
131 citations
Book•
31 Jan 1994
TL;DR: The KOAN/ANAGRAM II results allowed us to assess the importance of knowing the geometry of the path chosen and the strategy chosen to minimize the number of obstacles on the route.
Abstract: List of Figures. List of Tables. Preface. 1. Introduction. 2. Basic Placement. 3. Topological Placement. 4. Geometry Sharing Placement. 5. Line-Expansion Routing. 6. Integrated Rerouting. 7. Symmetric Routing. 8. Crosstalk Avoidance Routing. 9. Additional KOAN/ANAGRAM II Results. 10. Conclusions and Future Work. Subject Index.
119 citations
"Improved method of cell placement w..." refers background in this paper
...Improved Method of Cell Placement with Symmetry Constraints for Analog IC Layout Design Shinichi Kouda Chikaaki Kodama Kunihiro Fujiyoshi Department of Electrical and Electronic Engineering Tokyo University of Agriculture and Technology 2-24-16 Nakacho Koganei-shi Tokyo, 184-8588 Japan kouda@fjlab.ei.tuat.ac.jp, kodamada@fjlab.ei.tuat.ac.jp, fujiyosi@cc.tuat.ac.jp ABSTRACT Recently, it is often required in high performance analog IC design that some cells are placed symmetrically to horizontal or vertical axis....
[...]
...…and Technology 2-24-16 Nakacho Koganei-shi Tokyo, 184-8588 Japan kouda@fjlab.ei.tuat.ac.jp, kodamada@fjlab.ei.tuat.ac.jp, fujiyosi@cc.tuat.ac.jp ABSTRACT Recently, it is often required in high performance analog IC design that some cells are placed symmetrically to horizontal or vertical axis....
[...]
TL;DR: This paper addresses the problem of device-level placement for analog layout by using a more recent topological representation called sequence-pair, which has the advantage of not being restricted to slicing floorplan topologies.
Abstract: This paper addresses the problem of device-level placement for analog layout, focusing mainly on symmetry-related aspects. Different from most of the existent analog placement approaches, employing basically simulated annealing optimization algorithms operating on flat (absolute) spatial representations, our model uses a more recent topological representation called sequence-pair, which has the advantage of not being restricted to slicing floorplan topologies. In this paper, we explain how specific features essential to analog placement, such as the ability to deal with complex symmetry constraints (for instance, an arbitrary number of symmetry groups of cells), can be easily handled by employing the sequence-pair representation. Several analog examples substantiate the effectiveness of our placement tool, which is already in use in an industrial environment.
109 citations
TL;DR: This paper presents a very simple and efficient O(n/sup 2/) algorithm to solve the sequence pair evaluation problem and shows that using a more sophisticated data structure, the algorithm can be implemented to run in O (n log log n) time.
Abstract: Murata et al (1996) introduced an elegant representation of block placement called sequence pair All block-placement algorithms that are based on sequence pairs use simulated annealing where the generation and evaluation of a large number of sequence pairs is required Therefore, a fast algorithm is needed to evaluate each generated sequence pair, ie, to translate the sequence pair to its corresponding block placement This paper presents a new approach to evaluate a sequence pair based on computing longest common subsequence in a pair of weighted sequences We present a very simple and efficient O(n/sup 2/) algorithm to solve the sequence pair evaluation problem We also show that using a more sophisticated data structure, the algorithm can be implemented to run in O (n log log n) time Both implementations of our algorithm are significantly faster than the previous O(n/sup 2/) graph-based algorithm For example, we achieve 60 /spl times/ speedup over the previous algorithm when input size n = 128 As a result, we can examine a million sequence pairs within one minute for typical input size of placement problems For all MCNC benchmark block-placement problems, we have obtained the best results ever reported in the literature (including those reported by algorithms based on O tree and B* tree) with significantly less runtime For example, the best known result for ami49 (368 mm/sup 2/) was obtained by a B*-tree-based algorithm using 4752 s and we obtained a better result (365 mm/sup 2/) in 31 s
83 citations