Improved read noise margin characteristics for single bit line SRAM cell using adiabatically operated word line
01 Mar 2017-pp 385-393
TL;DR: In this article, a new SRAM cell architecture has been proposed, which shows improvement in read noise margin and power dissipation in low power VLSI systems, while the conventional 6T SRAM cells incur overall power consumption of 1.061E-3 watt and the value of the read noise margin is 0.115.
Abstract: Background/Objectives: In the contemporary era, due to the rapid development in various low power VLSI circuits, the primary factors that affect the performance of the circuits are gaining much importance. The static random access memory (SRAM) is one of the significant circuits employed in low power VLSI systems. Many researchers continue focusing on efficient SRAM designs and towards increasing the stability of the SRAM cells. Generally, single-bit line SRAM cells are more stable than the dual bit-line SRAM cells. The stability of SRAM cells depends on certain factors, such as control over the word line voltage, leakage power and power dissipation during read/write operation. Nowadays, several low power techniques have been developed for increasing the stability of SRAM cells. One such a technique is the non-conventional method called as adiabatic or energy recovery technique. Application of this adiabatic technique in the operation of an SRAM cell can enhance the read noise margin, since it determines the stability of the SRAM cell. This adiabatic technique mainly works on the focus that the adiabatic logic circuits consume less power, conserves energy and reutilizes the charge from the circuit nodes. This paper also proposes a new SRAM cell which shows improvement in read noise margin. Methods/Statistical analysis: Cadence EDA tools have been employed for the simulations. Layouts of different SRAM cells have been made using 180nm and 45nm CMOS technology library. Read and write operation output, power calculation and read noise margin calculations are performed with the help of the cadence virtuoso tool. For calculating read noise margin, input-output characteristics graph of two cross coupled inverters are plotted, and the maximum value of the square in the graph provide the value for the read noise margin. Furthermore, comparisons of conventional SRAM cells with the proposed SRAM cell are discussed in terms of power dissipation and read-noise margin. Conclusion/improvement: The results of the proposed SRAM cell are compared with the conventional SRAM cells. The overall power consumption of the proposed SRAM cell is 1.061E-3 watt and the value of the read noise margin is 0.115. On the other hand, the conventional 6T SRAM cell incur overall power consumption of 1.033E-3 watt with the read noise-margin of 0.121. The power dissipation of the proposed circuit is reduced by 3.1% when compared with the conventional 6T SRAM cell. Further, the proposed SRAM cell architecture has 52.17% better read noise margin when compared with the existing techniques.
Citations
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TL;DR: This paper combines multi threshold and fingering techniques to propose a modified 6T SRAM cell which has high speed, improved stability and low leakage current in stand-by mode of the memory cell.
Abstract: The semiconductor electronic industry is advancing at a very fast pace. The size of portable and handheld devices are shrinking day by day and the demand for longer battery backup is also increasing. With these requirements, the leakage power in stand-by mode becomes a critical concern for researchers. In most of these devices, memory is an integral part and its size also scales down as the device size is reduced. So, low power and high speed memory design is a prime concern. Another crucial factor is the stability of static random-access memory (SRAM) cells. This paper combines multi threshold and fingering techniques to propose a modified 6T SRAM cell which has high speed, improved stability and low leakage current in stand-by mode of the memory cell. The simulations are done using the Cadence Virtuoso tool on UMC 55 nm technology.
11 citations
30 Jul 2021
TL;DR: In this paper, the performance of the proposed 6T-SRAM cell using FINFET has been evaluated for this operation with low power domain, showing smaller SCEs, ultra-small acceptable time and stability.
Abstract: In this paper deals with simulation of FINFET device and subsequent application to a design of 6 Transistor Static RAM cell with FINFET as well as analysis of design issues and accomplishment metrics of advanced SRAM cells. As an initiation, the performance of the suggested 6T-SRAM cell using FINFET has been evaluated for this operation with low power domain, showing smaller SCEs, ultra-small acceptable time and Hugh stability. The static noise margin, leakage current, power dissipation & sub threshold current of 6 Transistor Static RAM using FINFET have been compared with MOSFET 6 Transistor Static RAM cell at 45nm technology node. After the remarkable reduction in Leakage current and power reduction, the same approach is then implemented to advanced SRAM cells. We have compared various advanced proposed SRAM cells using FINFET with the conventional advanced MOSFET with Static RAM. The significant leakage reduction have been observed when anyone switch from conventional MOSFET’s to FINFET’s. Leakage current for conventional MOSFET’s based 7T, 8T, 9T, 10T, 11T & 12T is 74.99 pA, 70.22 pA, 74.83 pA, 67.63 pA, 74.71pA, 63.56 pA and 73.96 pA respectively which have been reduced to 76.550 fA, 76.150 fA, 74.302 fA, 74.012 fA, 70.856 fA and 70.423 fA respectively for advanced FINFET based SRAM cells. Power dissipation for conventional MOSFET based 7, 8, 9, 10, 11& 12Transistor is 81.51nW, 80.77nW, 81.47nW, 79.47nW, 81.39nW, 78.59nW and 81.27nW respectively which have reduced to 9.972nW, 9.815nW, 9.565nW, 9.432nW, 9.148nW and 9.046nW respectively for advanced FINFET based SRAM cells.
6 citations
01 Oct 2018
TL;DR: This paper proposes a FinFET based differential $10T$ SRAM cell using Drowsy Cache architecture for leakage power reduction at 45nm technology node and presents supply voltage management technique for designing a low-power and variability-aware SRAMcell.
Abstract: On-chip SRAM array occupies a large area in the microprocessor ICs. This enforces the technology to reach nano-scale domain. In this domain, minimizing the short channel effects, leakage current and improving reliability of memory cell are significant and challenging. FinFET device reduces the short channel effects, leakage current and enhances the performance of the SRAM cell at 45nm technology node and beyond. This paper presents supply voltage management technique for designing a low-power and variability-aware SRAM cell. In this paper, we propose a FinFET based differential $10T$ SRAM cell using Drowsy Cache architecture for leakage power reduction at 45nm technology node. The proposed differential $10 T$ SRAM permits bit interleaving with column-wise write access control, having differential read path, thus, improving reliability of the SRAM cell. The proposed circuit also restricts pseudoread problem, by allowing column-wise write in SRAM cell array. The simulation has been carried out on Cadence Virtuoso at 45nm technology node.
6 citations
Cites methods from "Improved read noise margin characte..."
...Adding two n-FinFET devices to a conventional 6T SRAM cell will be responsible for read mechanism without disturbing the internal node of the SRAM bit cell [13]....
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24 Oct 2022
TL;DR: In this article , a quasi-adiabatic logic is used to slow down the charging and discharging process to reduce the energy dissipation and power consumption of SRAM cells, which is more effective for ultra low power applications where low power consumption is more prioritized than speed.
Abstract: Static Random Access Memory (SRAM) is a part of physical memory which is volatile, faster and power hungry. It draws a significant amount of power in comparison to other components of a computer, which is why reducing power consumption of SRAM contributes to the reduction of power consumption of overall system. Different circuit design techniques are introduced so far, to lower the power consumption. Adiabatic is a promising circuit design technique for low power VLSI design. Primarily, adiabatic logic can be divided into two kinds; Asymptotically adiabatic logic and Quasi-adiabatic logic [1]. In this paper, adiabatic is used to mean quasi-adiabatic. The main principle of adiabatic logic is to slowing down the charging and discharging process to reduce the energy dissipation and power consumption. Adiabatic Logic is more effective for the ultra-low power applications where low power consumption is more prioritized than speed. In this paper, a SRAM cell is proposed using a novel Quasi-Adiabatic Logic which draws less power than its predecessors. Simulations are performed on Cadence Virtuoso using gpdk090.
References
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Book•
01 Jan 1993
247 citations
"Improved read noise margin characte..." refers background or methods in this paper
...A plethora of new techniques have been developed for power reduction in memory elements such as the SRAM, so that the memory cell incurs the least possible power dissipation [5]....
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...The adiabatic logic can be explained using the Positive Feedback Adiabatic Logic (PFAL) shown in Fig 1(a) [5]....
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...required for the timing and cascading of the adiabatic gates [5]....
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...In addition to the above methods, one more efficient way in reducing power dissipation is the use of adiabatic logic technique [5]....
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TL;DR: This brief shows that a conventional semi-custom design-flow based on a positive feedback adiabatic logic (PFAL) cell library allows any VLSI designer to design and verify complex adiAbatic systems in a short time and easy way, thus, enjoying the energy reduction benefits of adiABatic logic.
Abstract: This brief shows that a conventional semi-custom design-flow based on a positive feedback adiabatic logic (PFAL) cell library allows any VLSI designer to design and verify complex adiabatic systems (e.g., arithmetic units) in a short time and easy way, thus, enjoying the energy reduction benefits of adiabatic logic. A family of semi-custom PFAL carry lookahead adders and parallel multipliers were designed in a 0.6-/spl mu/m CMOS technology and verified. Post-layout simulations show that semi-custom adiabatic arithmetic units can save energy a factor 17 at 10 MHz and about 7 at 100 MHz, as compared to a logically equivalent static CMOS implementation. The energy saving obtained is also better if compared to other custom adiabatic circuit realizations and maintains high values (3/spl divide/6) even when the losses in power-clock generation are considered.
109 citations
TL;DR: The proposed 7T SRAM cell with differential write and single ended read operations working in the near-threshold region is proposed and may be considered as one of the better design choices for both high performance and low power applications.
61 citations
IBM1
TL;DR: In this article, the SRAM behavior of FinFET technology is investigated and compared with 90 nm node planar partially-depleted silicon-on-insulator (PD-SOI) technology.
Abstract: The SRAM behavior of FinFET technology is investigated and compared with 90 nm node planar partially-depleted silicon-on-insulator (PD-SOI) technology. Unique FinFET circuit behavior in SRAM applications, resulting from the near-ideal device characteristics, is demonstrated by full cell cross section simulation for the first time, and shows high performance and low active and standby power. SRAM stability is analyzed in detail, as compared to PD-SOI.
44 citations
TL;DR: The techniques known in literature for the design of SRAM structures with low standby leakage typically exploit an additional operation mode, named the sleep mode or the standby mode, which leads to higher dynamic energy consumption than the conventional approach.
Abstract: The techniques known in literature for the design of SRAM structures with low standby leakage typically exploit an additional operation mode, named the sleep mode or the standby mode. In this paper, existing low leakage SRAM structures are analyzed by several SPEC2000 benchmarks. As expected, the examined SRAM architectures have static power consumption lower than the conventional 6-T SRAM cell. However, the additional activities performed to enter and to exit the sleep mode also lead to higher dynamic energy. Our study demonstrates that, due to this, the overall energy consumption achieved by the known low-leakage techniques is greater than the conventional approach. In the second part of this paper, a novel low-leakage SRAM cell is presented. The proposed structure establishes when to enter and to exit the sleep mode, on the basis of the data stored in it, without introducing time and energy penalties with respect to the conventional 6-T cell. The new SRAM structure was realized using the UMC 0.18-mum, 1.8-V, and the ST 90-nm 1-V CMOS technologies. Tests performed with a set of SPEC2000 benchmarks have shown that the proposed approach is actually energy efficient
31 citations