Improvements to a microelectronic design and fabrication course
TL;DR: Improvements made to a complimentary metal-oxide-semiconductor fabrication laboratory course to increase student learning and student impact (enrollment).
Abstract: This paper presents improvements made to a complimentary metal-oxide-semiconductor (CMOS) fabrication laboratory course to increase student learning and student impact (enrollment). The three main improvements to the course discussed include: 1) use of a two-mask MOS process that significantly reduced the time students took previously to design, fabricate, and verify the electrical properties of a metal-oxide-semiconductor field-effect transistor (MOSFET) process; 2) students' use of a semicustom integrated circuit (IC) design that significantly reduced the average design and processing time of previous years; and 3) development and implementation of a system of course prerequisites, which allowed a larger number of students to enroll in the course.
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TL;DR: In this paper, a 0.14 µm CMOS transistor with two levels of interconnection was designed and simulated to investigate its functionality and characteristics, and a scaling factor of 0.93 was applied to the transistor's effective channel length, the density of ion implantation for threshold voltage adjustment, and the gate oxide thickness.
Abstract: A 0.14 µm CMOS transistor with two levels of interconnection was designed and simulated to investigate its functionality and characteristics. ATHENA and ATLAS simulators were used to simulate the fabrication process and to validate the electrical characteristics, respectively. A scaling factor of 0.93 was applied to a 0.13 µm CMOS. The parameters being scaled are the effective channel length, the density of ion implantation for threshold voltage (Vth) adjustment, and the gate oxide thickness. In order to minimize high field effects, the following additional techniques were implemented: shallow trench isolation, sidewall spacer deposition, silicide formation, lightly doped drain implantation, and retrograde well implantation. The results show that drain current (ID) increases as the levels of interconnection increases. The important parameters for NMOS and PMOS were measured. For NMOS, the gate length (Lg) is 0.133 µm, Vth is 0.343138 V, and the gate oxide thickness (Tox) is 3.46138 nm. For PMOS, Lg is 0.133 µm, Vth is −0.378108 V, and Tox is 3.46167 nm. These parameters were validated and the device was proven to be operational.
17 citations
TL;DR: The MEMSlab course provides students at theETH Zurich with their sole opportunity to experience clean room microfabrication through a structured course setting, since there are no other solid-state device fabrication laboratory courses offered at the ETH Zurich.
Abstract: A microelectro-mechanical systems (MEMS) laboratory course (MEMSlab) in the Mechanical and Process Engineering Department at the Swiss Federal Institute of Technology (ETH Zurich), is presented. The course has been taught for four years and has been attended primarily by Master's students from mechanical and electrical engineering; since fall 2006, the course has been required within the Master of Micro and Nanosystems curriculum. Students participating in the MEMSlab course learn the operational principles of comb-structure accelerometers, as well as how to fabricate, package, and test single-axis accelerometers, thereby being exposed to the multiple disciplines and practical topics that are involved in the production of MEMS and microelectronics. Based upon the course assessments, which are summarized and discussed, one of the benefits of MEMSlab is the course format. This format, which includes a dedicated course text, referred to as the ldquoscript,rdquo and two introductory lecture sessions, has allowed students without prior semiconductor physics or process experience to participate fully in the course and to learn the major elements of MEMS fabrication. The MEMSlab course provides students at the ETH Zurich with their sole opportunity to experience clean room microfabrication through a structured course setting, since there are no other solid-state device fabrication laboratory courses offered at the ETH Zurich.
12 citations
Cites background from "Improvements to a microelectronic d..."
...Packaging is not typically addressed in microelectronic and MEMS fabrication courses [14]–[16]....
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TL;DR: The laboratory design, its impact on student experiences, and possible improvements and extensions are discussed.
Abstract: A laboratory-based class in flat-panel display technology is presented. The course introduces fundamental concepts of display systems and reinforces these concepts through the fabrication of three display devices-an inorganic electroluminescent seven-segment display, a dot-matrix organic light-emitting diode (OLED) display, and a dot-matrix liquid crystal display (LCD). Instead of fabricating a device over multiple laboratory sessions, students fabricate a functional device in a single session. This approach to teaching fabrication provides students immediate results, can accommodate students with disparate backgrounds, and can be easily adapted and expanded. This paper discusses the laboratory design, its impact on student experiences, and possible improvements and extensions.
12 citations
Cites background from "Improvements to a microelectronic d..."
...Many fabrication processes are quite time-consuming, which limits the amount of time for other, more instructive activities [1]....
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TL;DR: In this paper, the authors suggest some of the methods that can be implemented in engineering institutes to improve student laboratory experiences and also present the study of usage of online tools and rubric based laboratory assessment methodology adopted in electronics engineering course.
Abstract: Laboratory classes are integral part of an engineering course. Laboratory sessions are primarily designed to develop proficiency in technical skills, provide an opportunity to place theory in context, develop critical thinking skills and promote enquiry based learning. Laboratory experiences will be paramount in developing our students as independent learners, researchers, critical thinkers and generators of knowledge. There are several reforms need to be implemented to improve student laboratory experiences. This paper suggests some of the methods that can be implemented in engineering institutes. This paper also presents the study of usage of online tools and rubric based laboratory assessment methodology adopted in electronics engineering course.
9 citations
TL;DR: This work describes a novel, first-year graduate-level analog integrated circuit (IC) design course, which teaches students analog circuit design; an external manufacturer then produces their designs in three different silicon chips.
Abstract: This work describes a novel, first-year graduate-level analog integrated circuit (IC) design course. The course teaches students analog circuit design; an external manufacturer then produces their designs in three different silicon chips. The students, working in pairs, then test these chips to verify their success. All work is completed within one semester, and the grading cycle in the most recent offering of the course extended from September 2007 to February 2008, when there were 10 students enrolled. The manufacturer's shuttle cycle is 3.5 months. Most students in the course have only a college-level electronics background. The manufacturing process is Taiwan Semiconductor Manufacturing Company's (TSMC) 0.35 ?m CMOS Mixed-Signal 2P4M Polycide 3.3/5 V. The three successful chips consist of a voltage controlled oscillator, a high-performance differential amplifier, and a temperature-independent voltage reference generator. Section VI describes assessment and student feedback as well as proposed course improvement.
5 citations
Cites background from "Improvements to a microelectronic d..."
...designed a course that includes microelectronic design and fabrication [6] and has a fabrication focus, so design complexity strongly depended on students’ previous design experience....
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References
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01 Jan 1994
TL;DR: BiCMOS analogue building blocks sampled-data signal processing continuous-time signal processing current-mode signal processing analogue VLSI neural information processing data converters statistical modelling and simulation of analogue analogue CAD interconnects in analogue V LSI analogueVLSI design-for-test analogue integrated sensors.
Abstract: CMOS analogue building blocks BiCMOS analogue building blocks sampled-data signal processing continuous-time signal processing current-mode signal processing analogue VLSI neural information processing data converters statistical modelling and simulation of analogue analogue CAD interconnects in analogue VLSI analogue VLSI design-for-test analogue integrated sensors.
329 citations
"Improvements to a microelectronic d..." refers methods in this paper
...We did this by having students enrolled in the course act as an IC foundry[8], [9] for other class designs using our own Gate Array (Figure 1, and Figure 2), or Analog Leaf Cell[10] (Figure 3, and Figure 4) semi-custom environments....
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...[10] M....
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TL;DR: In this article, it is pointed out that the few milestones related in this article are only those that at the present time the writer feels are more important, without implying completeness or even absolute soundness in his judgment in selecting them.
Abstract: T HAS been less than seventeen years since D. Kahng and M. M. Atalla [l] of Bell Telephone Laboratories reported the first demonstration of an Si-Si02 MOS transistor. Even so, the annual sales of MOS based semiconductor components are expected to surpass one billion dollars in the U.S. alone. The impact on our daily lives imparted by these MOS based IC’s is just beginning to be felt. This tremendous explosion has been caused by many innovations and countless numbers of perhaps small but indispensable contributions by many unsung heroes. It is clear then that to list every single landmark, every twist and turn on the road would be just about impossible, even if one had unlimited time to dig into the history and unlimited space in this issue to describe them. It is hoped then that readers will understand that the few milestones related in this article are only those that at the present time the writer feels are more important, without implying completeness or even absolute soundness in his judgment in selecting them. It should also be remarked that what can now be recognized as the more significant milestones did not necessarily stand out and appear so at the times they occurred. Long before the invention of the transistor, the so-called “field. effect,” that is, a conductance change in a solid induced by application of transverse electric field, was the subject of intensive studies by various people. In fact, in the course of these studies, the discovery of transistor action itself was made [2]. As early as the 1920’s and 1930’s, proposals [3], [4] on amplifying devices based on “field effect” were made, however, with little apparent understanding of the physical phenomena. An unequivocal demonstration of the field effect was made by Shockley and Pearson in 1948 in their classic paper [5] in which they showed that an appreciable modulation of conductance in the surface region of a semiconductor occurred. The “field effect“ was subsequently applied to various but essentially similar amplifying device configurations by numerous people. These devices, however, relied on what was recognized as majority (carrier modulation. That is, the transverse electric field caused the majority carrier density to be modulated in a semiconductor bar which in turn resulted in conductance changes between two suitably located ohmic contacts. It is straightforward to show that useful devices based on this principle are achievable only under severe geometrical restrictions. Namely, the ratio
117 citations
"Improvements to a microelectronic d..." refers methods in this paper
...The two-mask NMOS or PMOS process was based on an aluminum gate [3], with spin on glass as a dopant source and a gate that overlaps the source and drain....
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TL;DR: In this paper, various technologies for contacts of Al on n+Si have been experimentally investigated, particularly in view of their suitability to very shallow np junctions, and special test patterns have been used to measure the contact resistivity, while diodes reverse current density has been checked to evaluate the junction leakage induced by the aluminum-silicon interaction during sintering.
Abstract: In this work various technologies for contacts of Al on n+Si have been experimentally investigated, particularly in view of their suitability to very shallow np junctions.
Special test-patterns have been used to measure the contact resistivity, while diodes reverse current density has been checked to evaluate the junction leakage induced by the aluminum-silicon interaction during sintering.
Best results are obtained by depositing a thin polysilicon layer on the front surface before the doping process and the Al evaporation. In this case both the requirements of low contact resistivity (< 10−4 ohm · cm2) and low junction leakage current are satisfied. Comparison with the conventional Al/Si and AgTi/Si ohmic contacts has been performed.
49 citations
"Improvements to a microelectronic d..." refers methods in this paper
...(A silicon/aluminum alloy was used to prevent junction spiking which increases the contact resistance [5]....
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12 Jun 1989
TL;DR: Rochester Institute of Technology has established a factory operation within its cleanroom facility as mentioned in this paper, which coexists with class laboratory instruction and research, and supports a variety of processes such as NMOS and bipolar.
Abstract: Rochester Institute of Technology has established a factory operation within its cleanroom facility. The factory coexists with class laboratory instruction and research. About one lot per week is released into the factory, and processing is completed automatically by paid student operators several weeks later. The customers for the factory are students and faculty involved in VLSI design courses in electrical engineering or computer engineering. Other customers include microelectronic engineering faculty and staff and graduate students from a variety of programs. The factory supports a variety of processes such as NMOS and bipolar. The organization and operation of this factory are described. >
18 citations
"Improvements to a microelectronic d..." refers methods in this paper
...This expansion was achieved by having students enrolled in the course act as an IC foundry [8], [9] for other class designs using the gate array (see Figs....
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TL;DR: Ten principles that should be of use in connecting the graduates of today with the engineering careers of tomorrow are proposed.
Abstract: This paper looks at changes in the education of engineers made necessary by unprecedented challenges within the semiconductor industry, from the perspective of a not-for-profit consortium of semiconductor manufacturers. To design and implement curricula to serve as a basis for the 40-year career of engineering graduates is a daunting challenge in this rapidly evolving environment. The authors propose ten principles that should be of use in connecting the graduates of today with the engineering careers of tomorrow.
8 citations
"Improvements to a microelectronic d..." refers background in this paper
...This side effect was actually an advantage because employees of semiconductor manufacturing or IC design companies will increasingly have to work in an interdisciplinary environment [7]....
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