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Proceedings ArticleDOI

Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers

Norman P. Jouppi
- Vol. 18, pp 364-373
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TLDR
In this article, a hardware technique to improve the performance of caches is presented, where a small fully-associative cache between a cache and its refill path is used to place prefetched data and not in the cache.
Abstract
Projections of computer technology forecast processors with peak performance of 1,000 MIPS in the relatively near future. These processors could easily lose half or more of their performance in the memory hierarchy if the hierarchy design is based on conventional caching techniques. This paper presents hardware techniques to improve the performance of caches.Miss caching places a small fully-associative cache between a cache and its refill path. Misses in the cache that hit in the miss cache have only a one cycle miss penalty, as opposed to a many cycle miss penalty without the miss cache. Small miss caches of 2 to 5 entries are shown to be very effective in removing mapping conflict misses in first-level direct-mapped caches.Victim caching is an improvement to miss caching that loads the small fully-associative cache with the victim of a miss and not the requested line. Small victim caches of 1 to 5 entries are even more effective at removing conflict misses than miss caching.Stream buffers prefetch cache lines starting at a cache miss address. The prefetched data is placed in the buffer and not in the cache. Stream buffers are useful in removing capacity and compulsory cache misses, as well as some instruction cache conflict misses. Stream buffers are more effective than previously investigated prefetch techniques at using the next slower level in the memory hierarchy when it is pipelined. An extension to the basic stream buffer, called multi-way stream buffers, is introduced. Multi-way stream buffers are useful for prefetching along multiple intertwined data reference streams.Together, victim caches and stream buffers reduce the miss rate of the first level in the cache hierarchy by a factor of two to three on a set of six large benchmarks.

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Citations
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Proceedings ArticleDOI

Evaluation of Techniques to Improve Cache Access Uniformities

TL;DR: The research is investigating the use of multiple techniques within a processor core and across cores in multicore system to improve the performance of cache memory hierarchies and the conclusion is that, each application may benefit from a different technique and no single scheme works universally well for all applications.

Hardware and software mechanisms for reducing load latency

TL;DR: Four novel load latency reduction techniques, each targeting a different component of load latency: address calculation, data cache access, address translation, and data cache misses are contributed.
Dissertation

Managing Memory for Power, Performance, and Thermal Efficiency

TL;DR: This work introduces and discusses several new application-transparent, memory management algorithms as well as a formal analytical model of a power-state control system rooted in classical control theory developed to proportionally scale memory capacity with application demand.
Proceedings ArticleDOI

Direct-mapped versus set-associative pipelined caches

TL;DR: C cache pip elining allows to reach the same pro cessor cycle time with a set-asso ciative cache or a direct-mapp ed cache with the same pip eline depth.
Dissertation

Reducing Memory Latency by Improving Resource Utilization

TL;DR: This work attacks a DRAM macro made by Hwang et.
References
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Journal ArticleDOI

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TL;DR: Specific aspects of cache memories investigated include: the cache fetch algorithm (demand versus prefetch), the placement and replacement algorithms, line size, store-through versus copy-back updating of main memory, cold-start versus warm-start miss ratios, mulhcache consistency, the effect of input /output through the cache, the behavior of split data/instruction caches, and cache size.

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Journal ArticleDOI

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Journal ArticleDOI

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Proceedings ArticleDOI

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TL;DR: The inclusion property is essential in reducing the cache coherence complexity for multiprocessors with multilevel cache hierarchies and a new inclusion-coherence mechanism for two-level bus-based architectures is proposed.