In-system constrained-random stimuli generation for post-silicon validation

doi:10.1109/TEST.2012.6401541

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In-system constrained-random stimuli generation for post-silicon validation

Proceedings Article•DOI•

In-system constrained-random stimuli generation for post-silicon validation

Adam B. Kinsman¹, Ho Fai Ko¹, Nicola Nicolici¹•Institutions (1)

McMaster University¹

05 Nov 2012-pp 1-10

TL;DR: This paper introduces a structured methodology for porting in-system the constrained-random stimuli generation aspect from a pre-silicon verification environment.

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Abstract: When generating the verification stimuli in a pre-silicon environment, the primary objectives are to reduce the simulation time and the pattern count for achieving the target coverage goals. In a hardware environment, because an increase in the number of stimuli is inherently compensated by the advantage of real-time execution, the objective augments to considering hardware complexity when designing in-system stimuli generators that must operate according to user-programmable constraints. In this paper we introduce a structured methodology for porting in-system the constrained-random stimuli generation aspect from a pre-silicon verification environment.

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Proceedings Article•DOI•

On-chip stimuli generation for post-silicon validation

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Nicola Nicolici¹•Institutions (1)

McMaster University¹

01 Nov 2012

TL;DR: This paper motivates the need for developing structured methods for porting the controllability aspects of pre-silicon verification into post- silicon validation environments.

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Abstract: In contrast to pre-silicon verification environments, insystem validation is not strongly constrained by the number of stimuli that can be applied; rather, the quality of the patterns, as well as the observation of the events of interest are the real concern. This paper motivates the need for developing structured methods for porting the controllability aspects of pre-silicon verification into post-silicon validation environments. Use cases and challenges for such methods are outlined.

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9 citations

Journal Article•DOI•

Generating Cyclic-Random Sequences in a Constrained Space for In-System Validation

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Xiaobing Shi¹, Nicola Nicolici¹•Institutions (1)

McMaster University¹

01 Dec 2016-IEEE Transactions on Computers

TL;DR: This paper presents a new method, including both software algorithms and on-chip hardware structures, for in-system constrained-random generation of stimuli sequences that are uniformly distributed, and is the first time it is shown how such feature can be ported to hardware environments.

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Abstract: The constrained-random methodology is widely used during the pre-silicon verification of very-large scale integrated circuits. Recently, research efforts have been made to support the application of constrained-random patterns during the post-silicon validation stage. In this paper, we present a new method, including both software algorithms and on-chip hardware structures, for in-system constrained-random generation of stimuli sequences that are uniformly distributed. More specifically, we facilitate in-system application of constrained-random sequences that are cyclic-random, i.e., all the valid values from the user-constrained space are generated only once before the entire sample space is exhausted. While software simulation environments commonly support this feature, e.g., randc in SystemVerilog, to the best of our knowledge this is the first time it is shown how such feature can be ported to hardware environments.

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8 citations

Cites background or methods from "In-system constrained-random stimul..."

...It is also worth noting that the existing reseeding-based methods [15], [18] for post-silicon validation do not provide any control for the stimuli distribution....
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...It is important to note that a thorough comparisons of cube-masking methods against reseeding-basedmethods [15], [18] has been provided in [16], [19], [20]....
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...The on-chip area for [16], [19] do not depend on the LFSR length (unlike [15], [18]),...
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...The methods from [15], [18] proposed to represent the original constraints (written in pre-silicon verification environments) by an...
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Proceedings Article•DOI•

Hardware-efficient on-chip generation of time-extensive constrained-random sequences for in-system validation

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Adam B. Kinsman¹, Ho Fai Ko¹, Nicola Nicolici¹•Institutions (1)

McMaster University¹

29 May 2013

TL;DR: This work advances the concept of porting constrained-random stimuli from a pre-silicon verification environment to in- system validation by improving both the hardware efficiency and the duration of in-system validation experiments.

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Abstract: Linear Feedback Shift Registers (LFSRs) have been extensively used for compressed manufacturing test. They have been recently employed as a foundation for porting constrained-random stimuli from a pre-silicon verification environment to in-system validation. This work advances this concept by improving both the hardware efficiency and the duration of in-system validation experiments.

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8 citations

Cites background or methods from "In-system constrained-random stimul..."

...It should be noted that in the same way as reported in [9], the goal of these experiments is to show how long runs of constrainedrandom stimuli can be generated on-chip efficiently in real-time....
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...The same end is achieved by the architecture proposed in [9], however, that approach loads all the basis vectors into registers which are selectively masked before summation by the bits which have value 0 of their equivalent to our Basis counter....
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...Thus, instead of requiring a large register array that scales quadratically with the LFSR size (as in [9]), only a few support registers are required, with the complexity being pushed into the addressing logic and the far greater number of accesses required to the memory....
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...As mentioned above, a key insight for greater efficiency of the architecture for expansion is a Gray-code like traversal of the set of all combinations of the basis vectors as opposed to a simple linear one, where more than one basis vector must be added / removed to obtain an updated seed, as done by [9]....
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...The basic idea from [9] is to map the functionally-compliant sequences onto linear-feedback shift registers (LFSRs)....
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Proceedings Article•DOI•

On-chip constrained random stimuli generation for post-silicon validation using compact masks

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Xiaobing Shi¹, Nicola Nicolici¹•Institutions (1)

McMaster University¹

01 Oct 2014

TL;DR: A new method to design constrained random stimuli generators, which are programmable and can be placed on-chip to generate extensive random, yet functionally-compliant, sequences for real-time/in-system validation.

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Abstract: During post-silicon validation a large number of constrained random stimuli are applied to expose the subtle design errors that have escaped to the silicon prototypes. In this paper we present a new method to design constrained random stimuli generators, which are programmable and can be placed on-chip to generate extensive random, yet functionally-compliant, sequences for real-time/in-system validation. The basic idea is to translate the constraints for constrained-random variables into binary cubes, whose specified values are used as masks to correct random sequences. To reduce the volume of data needed to be placed on-chip, the cubes are efficiently encoded and expanded in real-time. Experimental results confirm the effectiveness of this new method when compared against the prior work on the topic.

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6 citations

Journal Article•DOI•

On-Chip Cube-Based Constrained-Random Stimuli Generation for Post-Silicon Validation

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Xiaobing Shi¹, Nicola Nicolici¹•Institutions (1)

McMaster University¹

01 Jun 2016-IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

TL;DR: A methodology to design constrained-random stimuli generators, which are placed on-chip and are configurable at design-time to generate in-system functionally-compliant stimuli subject to user-programmable constraints provided at validation time.

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Abstract: Post-silicon validation is critical for exposing subtle design errors that have escaped to the silicon prototypes. Its effectiveness is conditioned by in-system application of a large volume of functionally-compliant stimuli. In this paper, we present a methodology to design constrained-random stimuli generators, which are placed on-chip and are configurable at design-time to generate in-system functionally-compliant stimuli subject to user-programmable constraints provided at validation time. Central to our method is a cube-based representation of constraints. These cubes are used as masks that force pseudo-random sequences to map onto functionally-compliant stimuli. To reduce the on-chip storage requirements, masks are compressed at design-time and expanded on-the-fly at validation time using decompression circuitry. Experimental results evaluate the impact of our method on the requirements for on-chip logic and memory resources.

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6 citations

Cites background or methods from "In-system constrained-random stimul..."

...It should also be noted that in the flow from Fig....
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...Consider the case of generating stimuli containing two 4-bit signals a and b with the constraint a ≥ b....
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...The constraints on the operands can be updated during the verification process, so as to focus on the suspicious ranges where the division calculation might be incorrectly implemented....
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...Both methods from [14] and [15] and the preliminary versions of our method [28], [29], translate the user-defined constraints into an equivalent set of cubes as shown in Fig....
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References

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Journal Article•DOI•

Graph-Based Algorithms for Boolean Function Manipulation

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Bryant¹•Institutions (1)

Carnegie Mellon University¹

01 Aug 1986-IEEE Transactions on Computers

TL;DR: In this paper, the authors present a data structure for representing Boolean functions and an associated set of manipulation algorithms, which have time complexity proportional to the sizes of the graphs being operated on, and hence are quite efficient as long as the graphs do not grow too large.

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Abstract: In this paper we present a new data structure for representing Boolean functions and an associated set of manipulation algorithms. Functions are represented by directed, acyclic graphs in a manner similar to the representations introduced by Lee [1] and Akers [2], but with further restrictions on the ordering of decision variables in the graph. Although a function requires, in the worst case, a graph of size exponential in the number of arguments, many of the functions encountered in typical applications have a more reasonable representation. Our algorithms have time complexity proportional to the sizes of the graphs being operated on, and hence are quite efficient as long as the graphs do not grow too large. We present experimental results from applying these algorithms to problems in logic design verification that demonstrate the practicality of our approach.

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9,021 citations

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The complexity of theorem-proving procedures

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Stephen A. Cook

03 May 1971

TL;DR: It is shown that any recognition problem solved by a polynomial time-bounded nondeterministic Turing machine can be “reduced” to the problem of determining whether a given propositional formula is a tautology.

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Abstract: It is shown that any recognition problem solved by a polynomial time-bounded nondeterministic Turing machine can be “reduced” to the problem of determining whether a given propositional formula is a tautology. Here “reduced” means, roughly speaking, that the first problem can be solved deterministically in polynomial time provided an oracle is available for solving the second. From this notion of reducible, polynomial degrees of difficulty are defined, and it is shown that the problem of determining tautologyhood has the same polynomial degree as the problem of determining whether the first of two given graphs is isomorphic to a subgraph of the second. Other examples are discussed. A method of measuring the complexity of proof procedures for the predicate calculus is introduced and discussed.

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6,675 citations

"In-system constrained-random stimul..." refers background in this paper

...Solving a SAT problem is known to be NP-complete (Cook, 1971), nevertheless, many SAT algorithms have been developed that have been proven to be efficient in practical applications....
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Book Chapter•DOI•

An Extensible SAT-solver

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Niklas Een¹, Niklas Sörensson¹•Institutions (1)

Chalmers University of Technology¹

05 May 2003

TL;DR: This article presents a small, complete, and efficient SAT-solver in the style of conflict-driven learning, as exemplified by Chaff, and includes among other things a mechanism for adding arbitrary boolean constraints.

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Abstract: In this article, we present a small, complete, and efficient SAT-solver in the style of conflict-driven learning, as exemplified by Chaff. We aim to give sufficient details about implementation to enable the reader to construct his or her own solver in a very short time.This will allow users of SAT-solvers to make domain specific extensions or adaptions of current state-of-the-art SAT-techniques, to meet the needs of a particular application area. The presented solver is designed with this in mind, and includes among other things a mechanism for adding arbitrary boolean constraints. It also supports solving a series of related SAT-problems efficiently by an incremental SAT-interface.

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2,985 citations

"In-system constrained-random stimul..." refers methods in this paper

...An off-the-shelf solver [8] has been used for the SAT component, however it should be noted that scalability to the the larger SAT instances will require an integrated GF2/SAT hybrid solver when working with larger number of forced bits....
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...In order to search this space more efficiently, we capture this space as a SAT instance, and leverage the power of modern SAT solvers which perform learning over the solution space through techniques such as generating conflict clauses [8]....
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Book•

CMOS VLSI Design : A Circuits and Systems Perspective

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Neil Weste, David Money Harris

21 May 2004

TL;DR: The authors draw upon extensive industry and classroom experience to introduce todays most advanced and effective chip design practices, and present extensively updated coverage of every key element of VLSI design, and illuminate the latest design challenges with 65 nm process examples.

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Abstract: For both introductory and advanced courses in VLSI design, this authoritative, comprehensive textbook is highly accessible to beginners, yet offers unparalleled breadth and depth for more experienced readers. The Fourth Edition of CMOS VLSI Design: A Circuits and Systems perspective presents broad and in-depth coverage of the entire field of modern CMOS VLSI Design. The authors draw upon extensive industry and classroom experience to introduce todays most advanced and effective chip design practices. They present extensively updated coverage of every key element of VLSI design, and illuminate the latest design challenges with 65 nm process examples. This book contains unsurpassed circuit-level coverage, as well as a rich set of problems and worked examples that provide deep practical insight to readers at all levels.

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2,355 citations

"In-system constrained-random stimul..." refers background in this paper

...The design rules checking (DRC) and electrical rules checking (ERC) verify if geometrical distances needed for correct fabrication are respected (Weste and Harris, 2011)....
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Journal Article•DOI•

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01 May 1994-Journal of Logic Programming

TL;DR: This survey of CLP is to give a systematic description of the major trends in terms of common fundamental concepts and the three main parts cover the theory, implementation issues, and programming for applications.

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Abstract: Constraint Logic Programming (CLP) is a merger of two declarative paradigms: constraint solving and logic programming. Although a relatively new field, CLP has progressed in several quite different directions. In particular, the early fundamental concepts have been adapted to better serve in different areas of applications. In this survey of CLP, a primary goal is to give a systematic description of the major trends in terms of common fundamental concepts. The three main parts cover the theory, implementation issues, and programming for applications.

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1,571 citations

"In-system constrained-random stimul..." refers methods in this paper

...Some methods based on word-level constraints solving for high-level modelling have been proposed (Jaffar and Maher, 1994), however bit-level manipulation is eventually required whenever logic conditions arise....
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