Incremental Delta-Sigma ADCs: A Tutorial Review
TL;DR: Various design techniques for improving the energy-efficiency of the IADCs are described and intended to serve as a starting point for the development of a new energy-efficient IADC.
Abstract: In many sensor applications, a high-resolution analog-to-digital converter (ADC) is a key block. The use of an incremental delta-sigma ADC (IADC) is often well suited for such applications. While the energy-efficiency of IADCs has improved by several orders of magnitude over the past decade, the implementation of high performance IADCs, especially in battery-powered systems, is still challenging. This paper presents a tutorial review on energy-efficient IADCs and addresses the progress in this area. This paper describes the fundamentals of IADCs and energy-efficient hybrid IADC architectures. Various design techniques for improving the energy-efficiency of the IADCs are described. This paper is intended to serve as a starting point for the development of a new energy-efficient IADC.
Citations
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22 Jan 2018
TL;DR: A micropower audio delta-sigma modulator is presented for mobile applications, which employs dynamic bias inverter based integrators, which maximizes both g m /I D ratio and slew rate while compensating PVT variations.
Abstract: A micropower audio delta-sigma modulator is presented for mobile applications. The modulator employs dynamic bias inverter based integrators, which maximizes both g m /I D ratio and slew rate while compensating PVT variations. A prototype modulator implemented in a 0.18pm CMOS process features a single-bit third-order topology. The modulator achieves 97.7dB SNDR, 98.6dB SNR, 100.5dB DR, and 105.8dB SFDR in a 20kHz audio band, while consuming only 300pW from a 1.8V supply. This corresponds to a state-of-the-art FoM of 178.7dB.
17 citations
01 Jan 2013
10 citations
TL;DR: This work proposes an ultra-low voltage, ultra- low power, inverter-based ΔΣ modulator with reduced finite-DC-gain sensitivity, and employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction.
Abstract: The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage ΔΣ modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based ΔΣ modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the CadenceTM design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources.
6 citations
TL;DR: In this paper, the effects of FIR feedback on the maximum stable amplitude of an incremental delta-sigma data converter are examined. But, the effect of FIR is limited in terms of the modulator's linearity and the quantizer's complexity.
Abstract: Incremental delta-sigma data converters are useful in applications where one ADC is needed to digitize multiple channels. They can be realized using single- or multi-bit feedback. In both cases, the use of FIR feedback is beneficial in terms of improving the modulator’s linearity, reducing the quantizer’s complexity, and mitigating the effects of clock jitter (in a continuous-time realization). In the incremental mode, however, the maximum stable amplitude of the ADC is severely impacted by FIR feedback. The reasons behind this are examined, and techniques that mitigate this problem are given. Circuit simulations of an example fourth-order single-bit incremental modulator with an eight-tap FIR DAC are given to illustrate the efficacy of the theory.
5 citations
TL;DR: In this article , a noise-shaping phase-switching technique on a sigma-delta modulated digital-to-analog converter (DAC) was proposed to realize a low-noise, high-linearity sinusoidal-wave generator.
Abstract: To develop a lower cost on-chip characterization solution for postsilicon validation, this article proposed a “noise-shaping phase-switching” technique on a sigma–delta modulated digital-to-analog converter (DAC) to realize a low-noise, high-linearity sinusoidal-wave generator. The proposed technique combines the fifth-order cascade of resonators with distributed feedback (CRFB) type delta–sigma modulation (DSM) and the two-way time-interleaving phase-switching harmonic distortion (HD) cancellation technique without additional cost. The theoretical analysis is verified with MATLAB and further implemented using a low-cost arbitrary waveform generator (AWG) as the output DAC. Compared with a nonideal 12-b DAC, the proposed technique achieved at least 2-dB enhancement in spurious-free dynamic range (SFDR) (measurement) while maintaining an improvement of at least 18 dB in the medium dynamic range (DR) (simulation) over the entire signal bandwidth.
5 citations
References
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Book•
08 Nov 2004
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
2,200 citations
TL;DR: A class of digital linear phase finite impulse response (FIR) filters for decimation and interpolation and use limited storage making them an economical alternative to conventional implementations for certain applications.
Abstract: A class of digital linear phase finite impulse response (FIR) filters for decimation (sampling rate decrease) and interpolation (sampling rate increase) are presented. They require no multipliers and use limited storage making them an economical alternative to conventional implementations for certain applications. A digital filter in this class consists of cascaded ideal integrator stages operating at a high sampling rate and an equal number of comb stages operating at a low sampling rate. Together, a single integrator-comb pair produces a uniform FIR. The number of cascaded integrator-comb pairs is chosen to meet design requirements for aliasing or imaging error. Design procedures and examples are given for both decimation and interpolation filters with the emphasis on frequency response and register width.
1,372 citations
"Incremental Delta-Sigma ADCs: A Tut..." refers background in this paper
...A Hogenauer sinc3 decimation filter [16] for a second-order modulator is shown in Fig....
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...(b) A decimation filter example (c) The Hogenauer third-order sinc filter [16]....
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TL;DR: In this article, a linear, tunable integrator for very high-frequency integrated filters can be made, which has good linearity properties and non-dominant poles in the gigahertz range owing to the absence of internal nodes.
Abstract: CMOS circuits for integrated analog filters at very high frequencies, based on transconductance-C integrators, are presented. First a differential transconductance element based on CMOS inverters is described. With this circuit a linear, tunable integrator for very-high-frequency integrated filters can be made. This integrator has good linearity properties and nondominant poles in the gigahertz range owing to the absence of internal nodes. The integrator has a tunable DC gain, resulting in a controllable integrator quality factor. Experimental results of a VHF CMOS transconductance-C low-pass filter realized in a 3- mu m CMOS process are given. Both the cutoff frequency and the quality factors can be tuned. The cutoff frequency was tuned from 22 to 98 MHz and the measured filter response is very close to the ideal response of the passive prototype filter. Furthermore, a novel circuit for automatically tuning the quality factors of integrated filters built with these transconductors is described. >
674 citations
"Incremental Delta-Sigma ADCs: A Tut..." refers background in this paper
...As a result, the PVT tolerances of the inverter-based amplifiers have been significantly improved with various techniques, such as current starving, dynamic biasing [33]–[36], [43]–[46], bodybiasing [47], [48], and adaptive supply-biasing [49]–[51]....
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TL;DR: In this paper, a /spl Delta/spl Sigma/ topology with reduced sensitivity to opamp nonlinearities is described, which is effective even for very low oversampling ratios, and can be used for any modulation order.
Abstract: A /spl Delta//spl Sigma/ topology with reduced sensitivity to opamp nonlinearities is described. The technique is effective even for very low oversampling ratios, and can be used for any modulation order. Techniques for reducing other nonideal effects are also proposed.
575 citations
"Incremental Delta-Sigma ADCs: A Tut..." refers background or methods in this paper
...2, the feed-forward loop filter only processes the shaped quantization noise [17]....
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...The feedforward with an input direct path is used as an example to illustrate the operation of IADC [7], [17], and other architectures can be derived similarly....
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TL;DR: It is shown how speed, resolution, and A/D complexity can be optimized for a given design, and how with some special digital filters improved speed/resolution ratio can be achieved.
Abstract: Analog-Digital (A/D) converters used in instrumentation and measurements often require high absolute accuracy, including very high linearity and negligible dc offset. The realization of high-resolution Nyquist-rate converters becomes very expensive when the resolution exceeds 16 bits. The conventional delta-sigma (/spl Delta//spl Sigma/) structures used in telecommunication and audio applications usually cannot satisfy the requirements of high absolute accuracy and very small offset. The incremental (or integrating) converter provides a solution for such measurement applications, as it has most advantages of the /spl Delta//spl Sigma/ converter, yet is capable of offset-free and accurate conversion. In this paper, theoretical and practical aspects of higher order incremental converters are discussed. The operating principles, topologies, specialized digital filter design methods, and circuit level issues are all addressed. It is shown how speed, resolution, and A/D complexity can be optimized for a given design, and how with some special digital filters improved speed/resolution ratio can be achieved. The theoretical results are verified by showing design examples and simulation results.
269 citations