Independent gate finfet sram cell using leakage reduction techniques
01 Jan 2014-
TL;DR: 6T SRAM cell is implemented using independent gate FinFET in which both the opposite side of gates are operated independently which provides better scalability to the SRAMcell and provides better performance.
Abstract: Scaling of devices in bulk CMOS technology contributes to short channel effects and increase in leakage. Static random access memory (SRAM) is needed to occupy 90% of the area of SoC. Since leakage becomes the important factor in SRAM cell, it is implemented using FinFET. FinFET devices became better alternative for deep submicron technologies. In this paper, 6T SRAM cell is implemented using independent gate FinFET in which both the opposite side of gates are operated independently which provides better scalability to the SRAM cell. The device is implemented using different leakage reduction techniques such as Multi threshold voltage, and Gated-VDD technique to reduce leakage current, power consumption in the SRAM cell and provides better performance. The Proposed FinFET based 6T SRAM cell has been designed using Cadence Virtuoso Tool, all the simulation results has been generated by Cadence SPECTRE simulator at 45nm Technology.
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18 Jan 2010
TL;DR: Gate work function and oxide thickness tuning to realize novel circuits using dual-Vth independent-gate FinFETs with independent gates to enable a new class of compact logic gates with higher expressive power and flexibility than conventional forms.
Abstract: This paper describes gate work function and oxide thickness tuning to realize novel circuits using dual-V th independent-gate FinFETs. Dual-V th FinFETs with independent gates enable series and parallel merge transformations in logic gates, realizing compact low power alternatives. Furthermore, they also enable the design of a new class of compact logic gates with higher expressive power and flexibility than conventional forms, e.g., implementing 12 unique Boolean functions using only four transistors. The gates are designed and calibrated using the University of Florida double-gate model into a technology library. Synthesis results for 14 benchmark circuits from the ISCAS and OpenSPARC suites indicate that on average, the enhanced library reduces delay, power, and area by 9%, 21%, and 27%, respectively, over a conventional library designed using FinFETs in 32nm technology.
32 citations
"Independent gate finfet sram cell u..." refers background in this paper
...…with short-channels (SCEs), not only very ultra-thin to keep the current drive is required but also very low VTH is required to maintain the device speed and VTH variations under control [3] as this effect can degrade the devices sub-threshold slope and cause changes in the threshold Voltage (VTH)....
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10 Mar 2008
TL;DR: This paper introduces a new approach for sleep transistor sizing which minimizes the total sleep transistor width for a coarse-grain multi-threshold CMOS circuit assuming a given standard cell and sleep transistor placement.
Abstract: Power gating is one of the most effective techniques in reducing the standby leakage current of VLSI circuits. In this paper we introduce a new approach for sleep transistor sizing which minimizes the total sleep transistor width for a coarse-grain multi-threshold CMOS circuit assuming a given standard cell and sleep transistor placement. First, the circuit is decomposed into a set of modules, each containing the set of logic cells that are closest to a sleep transistor cell. Next given an upper bound on the overall circuit speed degradation, the global timing slack is distributed among different clusters using a delay-budgeting. The slack distribution result is then used to size the sleep transistors such that the total sleep transistor width is minimized while accounting for the parasitic resistances of the virtual ground net. Results show that the proposed sizing algorithm produces sleep transistor sizes that are 40% smaller than those produced by previous approaches.
31 citations
TL;DR: In this paper, a simple model that takes into account the effect of threshold voltage and sub-threshold swing fluctuations and their correlation is proposed to study the drain-current mismatch of FinFETs in subthreshold, from both modeling and experimental point of view.
Abstract: In this paper, we study the drain-current mismatch of FinFETs in subthreshold, from both modeling and experimental point of view. We propose a simple model that takes into account the effect of threshold voltage and subthreshold swing fluctuations and their correlation. For long-channel devices (longer than a critical length LC), characterized by a subthreshold swing close to the ideal value, the overall current mismatch is dominated by threshold voltage fluctuations and, therefore, is gate voltage independent. The subthreshold swing fluctuations give a negligible effect on the drain-current mismatch and are uncorrelated with the threshold voltage fluctuations. For short-channel devices (shorter than a critical length LC), characterized by a strong dependence of subthreshold swing on the channel length, the overall current mismatch presents an additional relevant contribution associated with the subthreshold swing fluctuations. This component depends on the gate voltage overdrive and is ascribed to the gate line edge roughness, resulting in a partial correlation between threshold voltage and subthreshold swing fluctuations.
29 citations
17 Mar 2008
TL;DR: In this article, an independent-gate (IG) FinFET static memory cell with dynamic access transistor threshold voltage tuning is evaluated for statistical power and stability distributions under process parameter variations.
Abstract: A new six transistor (6T) FinFET static memory cell with dynamic access transistor threshold voltage tuning is evaluated in this paper for statistical power and stability distributions under process parameter variations. The independent-gate (IG) FinFET SRAM cell activates only one gate of the double-gate data access transistors during a read operation. The disturbance caused by the direct data access mechanism of the standard 6T SRAM cell topology is significantly reduced by dynamically increasing the threshold voltage of the access transistors. All the transistors in the presented SRAM cell are sized minimum without producing any data stability concerns. The average read static-noise-margin of the statistical samples with the independent gate bias technique is 82% higher as compared to the standard tied-gate FinFET SRAM cells under process variations. Furthermore, the IG-FinFET SRAM circuit reduces the average leakage power and the cell area by up to 53.3% and 17.5%, respectively, as compared to the standard tied-gate FinFET SRAM circuits sized for comparable data stability in a 32 nm FinFET technology.
19 citations
01 Jan 2011
TL;DR: A more printable notchless QP bulk SRAM cell layout is proposed to reduce lithographic variations, and is projected to achieve six-sigma yield (required for terabit-scale SRAM arrays) with a minimum operating voltage below 1 Volt.
Abstract: Continued planar bulk MOSFET scaling is becoming increasingly difficult due to increased random variation in transistor performance with decreasing gate length, and thereby scaling of SRAM using minimum-size transistors is further challenging. This dissertation will discuss various advanced MOSFET designs and their benefits for extending density and voltage scaling of static memory (SRAM) arrays. Using threedimensional (3-D) process and design simulations, transistor designs are optimized. Then, using an analytical compact model calibrated to the simulated transistor current-vs.-voltage characteristics, the performance and yield of six-transistor (6-T) SRAM cells are estimated. For a given cell area, fully depleted silicon-on-insulator (FD-SOI) MOSFET technology is projected to provide for significantly improved yield across a wide range of operating voltages, as compared with conventional planar bulk CMOS technology. Quasi-Planar (QP) bulk silicon MOSFETs are a lower-cost alternative and also can provide for improved SRAM yield. A more printable notchless QP bulk SRAM cell layout is proposed to reduce lithographic variations, and is projected to achieve six-sigma yield (required for terabit-scale SRAM arrays) with a minimum operating voltage below 1 Volt.
15 citations
"Independent gate finfet sram cell u..." refers background in this paper
...In cross coupled inverters, both the opposite side gates in pull up transistors are controlled independently to provide multi-threshold voltages and opposite gates in pull down transistors are tied to each other....
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