Journal ArticleDOI
Integral impact of PVT variation with NBTI degradation on dynamic and static SRAM performance metrics
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TLDR
In this article, the authors investigated the combined effect of negative bias temperature instability (NBTI) and process variability on the performance of CMOS technology and found that it is highly susceptible to ageing effects.Abstract:
Advanced CMOS technology is highly susceptible to ageing effects such as negative bias temperature instability (NBTI) and process variability. This article focuses on investigating the ‘combined im...read more
Citations
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Journal ArticleDOI
Design of Power Gated SRAM Cell for Reducing the NBTI Effect and Leakage Power Dissipation During the Hold Operation
Journal ArticleDOI
Design of Power Gated SRAM Cell for Reducing the NBTI Effect and Leakage Power Dissipation During the Hold Operation
Device Reliability Affecting Coding Schemes in Neuromorphic Circuits
TL;DR: In this article , the authors investigated the presence of fault/mismatches when the neuron spikes for different uniformly and randomly-distributed input strengths, and showed that the neuron circuit functions effectively for most of the applied uniformly-disciplined inputs, its detrimental effects were still very apparent in the randomly distributed inputs potentially impacting signal/information transmission in an SNN.
Impact of Reliability Issues and Process Variability in Neuromorphic Circuits
TL;DR: This work presents the degradation analysis of Axon Hillock (AH) and Simplified Leaky Integrate & Fire (SLIF) neuron circuits and analysed the impact of BTI, HCI and their combined effect on the circuit performance.
Proceedings ArticleDOI
Device Reliability Affecting Coding Schemes in Neuromorphic Circuits
TL;DR: In this paper , the authors investigate the presence of fault/mismatches when the neuron spikes for different uniformly and randomly-distributed input strengths, and they demonstrate that the neuron circuit functions effectively for most of the applied uniformly-disributed inputs, its detrimental effects were still very apparent in the randomly distributed inputs potentially impacting signal/information transmission in an SNN.
References
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Journal ArticleDOI
Static-noise margin analysis of MOS SRAM cells
TL;DR: In this article, the stability of both resistor-load (R-load) and full-CMOS SRAM cells is investigated analytically as well as by simulation, and explicit analytic expressions for the static-noise margin (SNM) as a function of device parameters and supply voltage are derived.
Journal ArticleDOI
The impact of intrinsic device fluctuations on CMOS SRAM cell stability
TL;DR: In this paper, the reduction in CMOS SRAM cell static noise margin due to intrinsic threshold voltage fluctuations in uniformly doped minimum-geometry cell MOSFETs is investigated using compact physical and stochastic models.
Journal ArticleDOI
Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies
TL;DR: This paper analyzes the read stability N-curve metrics and compares them with the commonly used static noise margin (SNM) metric defined by Seevinck, and demonstrates that the new metrics provide additional information in terms of current, which allows designing a more robust and stable cell.
Journal ArticleDOI
A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply
Kevin Zhang,Uddalak Bhattacharya,Zhanping Chen,Fatih Hamzaoglu,D. Murray,N. Vallepalli,Yih Wang,B. Zheng,M. Bohr +8 more
TL;DR: In this article, a column-based dynamic power supply has been integrated into a high-frequency 70-Mb SRAM design that is fabricated on a high performance 65-nm CMOS technology.
Proceedings ArticleDOI
Statistical variability and reliability in nanoscale FinFETs
TL;DR: In this paper, a comprehensive 3D simulation study of statistical variability and reliability in emerging, scaled FinFETs on SOI substrate with gate-lengths of 20nm, 14nm and 10nm and low channel doping is presented.