Journal ArticleDOI
Integrated circuit yield statistics
C.H. Stapper,F.M. Armstrong,K. Saji +2 more
- Vol. 71, Iss: 4, pp 453-470
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TLDR
In this paper, the random failure statistics for the yield of mass-produced semiconductor integrated circuits are derived by considering defect and fault formation during the manufacturing process, which allows the development of a yield theory that includes many models that have been used previously and also results in a practical control model for integrated circuit manufacturing.Abstract:
The random failure statistics for the yield of mass-produced semiconductor integrated circuits are derived by considering defect and fault formation during the manufacturing process. This approach allows the development of a yield theory that includes many models that have been used previously and also results in a practical control model for integrated circuit manufacturing. Some simpler formulations of yield theory that have been described in the literature are compared to the model. Application of the model to yield management are discussed and examples given.read more
Citations
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Journal ArticleDOI
Modeling of integrated circuit defect sensitivities
TL;DR: This paper treats the fundamentals of the defect models that have been used successfully at IBM for more than fifteen years, and the effects of very small defects are discussed first.
Proceedings ArticleDOI
Realistic Fault Modeling for VLSI Testing
TL;DR: It will be demonstrated that inadequate insight into the physics of processing defects and the manufacturing process may lead to inefficient testing of actual VLSI circuits.
Journal ArticleDOI
Defect tolerance in VLSI circuits: techniques and yield analysis
Israel Koren,Zahava Koren +1 more
TL;DR: A detailed survey of yield-enhancement techniques for very large-scale-integration (VLSI) circuits can be found in this article, where the authors provide a detailed survey and illustrate their use by describing the design of several representative defect-tolerant VLSI circuits.
Journal ArticleDOI
Detection of catastrophic faults in analog integrated circuits
L. Milor,V. Visvanathan +1 more
TL;DR: The construction of a set of measurements that detects many faulty circuits before specification testing is described, and its effectiveness in detecting faulty circuits is evaluated.
Journal ArticleDOI
Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits
TL;DR: Optimization of geometrical design rules, evaluation of VLSI IC artwork, and maximization of the wafer yield are discussed as examples illustrating applications and advantages of the proposed modeling technique.
References
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TL;DR: In this article, Lindley et al. make the less restrictive assumption that such a normal, homoscedastic, linear model is appropriate after some suitable transformation has been applied to the y's.
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An Inquiry into the Nature of Frequency Distributions Representative of Multiple Happenings with Particular Reference to the Occurrence of Multiple Attacks of Disease or of Repeated Accidents
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Cost-size optima of monolithic integrated circuits
TL;DR: In this article, a generalized cost-size relationship is derived for a monolithic circuit consisting of N identical components, taking into account variations in component density, yield, and assembly costs with N. The results indicate that when systems requirements make it desirable to include larger numbers of components in one package than the optimum for one monolith, wired-chip schemes are preferable to single monoliths, the optimum chip size being smaller than that for a simple monolith.