Book ChapterDOI

# Integrated CMOS sensor technologies for the CLIC tracker

27 Jun 2017-Vol. 213, pp 361-365

TL;DR: CMOS circuitry on a high resistivity epitaxial layer has been studied using the ALICE Investigator test-chip and a Technology Computer Aided Design based simulation chain has been developed to further explore the sensor technology.
Abstract: Integrated technologies are attractive candidates for an all silicon tracker at the proposed future multi-TeV linear $$\mathrm {e^{+} e^{-}}$$ collider CLIC. In this context CMOS circuitry on a high resistivity epitaxial layer has been studied using the ALICE Investigator test-chip. Test-beam campaigns have been performed to study the Investigator performance and a Technology Computer Aided Design based simulation chain has been developed to further explore the sensor technology.
Topics: CMOS sensor (53%)

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CLICdp-Conf-2017-011
27 June 2017
Integrated CMOS sensor technologies for the CLIC tracker
M. Munker
1)
On behalf of the CLICdp collaboration
CERN, Switzerland,
University of Bonn, Germany
Abstract
Integrated technologies are attractive candidates for an all silicon tracker at the proposed
future multi-TeV linear e
+
e
collider CLIC. In this context CMOS circuitry on a high res-
istivity epitaxial layer has been studied using the ALICE Investigator test-chip. Test-beam
campaigns have been performed to study the Investigator performance and a Technology
Computer Aided Design based simulation chain has been developed to further explore the
sensor technology.
Talk presented at International Conference on Technology and Instrumentation in Particle Physics 2017
(TIPP2017), Beijing, China, 22-26 May 2017
c
2017 CERN for the beneﬁt of the CLICdp Collaboration.
1
magdalena.munker@cern.ch

INTEGRATED CMOS SENSOR
TECHNOLOGIES FOR THE CLIC TRACKER
Magdalena Munker on behalf of the CLICdp collaboration
1
CERN magdalena.munker@cern.ch
2
University of Bonn
Abstract. Integrated technologies are attractive candidates for an all
silicon tracker at the proposed future multi-TeV linear e
+
e
collider
CLIC. In t h is context CMOS circuitry on a high resistivity epitaxial
layer has been studied using the ALICE Investigator test-chip. Test-beam
campaigns have been performed to stu d y the Investigator pe rform a n c e
and a Technology Computer Aided Design based simulation chain has
been developed to further explore the sensor technology.
1 Introduction
The Compact Linear Colli de r (CLIC) is an option for a future linear e
+
e
col-
lider at CERN in the post LHC era, reaching a centre of mass energy up to 3 TeV
[1, 2, 3, 4]. To perform highly precise physics measurements, a single point reso-
lution of 7 µm and a material budget of 1 2%X
0
per layer n ee d to be reached
in the large ar ea tracker detector. To suppress be am induced background par t i -
cles, a time stamping accuracy of 10 ns is required for the main tracker [2, 5].
A large surface ( 100 m
2
) all-silicon tracker is planned to address these require-
ments. Integrated technologies are promising candidates in view of large-scale
production and low material budget. Test beam campaigns to study the Investi-
gator High Resistivity (HR) CMOS test chip have been performed at the CERN
SPS with a 120 GeV pion beam. As a reference system, the CLICdp Timepix3
telescope has been used, providing an excellent tracking and timing resolution
on the Device Under Test (DUT) plane of 2 µm and 1 ns, respectively [6].
2 The Investigator chip
Within the ALICE ITS upgrade project, a fully monolithic chip, the ALPIDE
[7], has been developed in a 180 nm High Resistivity (HR) CMOS process (see
Figure 1). Using the same process, the Investigator test-chip has been developed
[8, 9]. Various pixel layouts are implemented in dierent mini-matrices with
8 8 pixels, to study the impact of the pixel layout on the performance. The
standard p r ocess h as been modiﬁed, inserting an additional n-layer (see Figure
2) to create a deep planar pn-ju nc ti on and achieve full lateral depletion of the
sensor. The output of the source foll ower of each individual pixel is connected
to a dedicated output buer with a rise time of 10 ns.

2
P
-
P
++
backside
Deep.P-well
N-well
P-MOS
N-MOS
Fig. 1. Investiga to r standard
process schematic cross section.
N
-
P
Deep'P-well
N-well
P-MOS
N-MOS
Fig. 2. Investigator modiﬁed
process schematic cross section.
The outpu t buers are read out by external ADCs, sampling the individual
pixel response with a f r eq ue nc y of 65 MHz [9]. The presented studies have been
performed for a mini -m at ri x with a pixel pitch of 28 µm and a bias voltage of
6 V, using chips with an epitaxial layer thickness of 18 µm for the standard, and
25 µm for the modiﬁed process.
3 Test beam data taking and reconstruction
If at least one pixel crosses a seed threshold, the ful l analogue waveform of all
8 8 pix el s is read out. In Figure 3, a typical waveform of a pixel with a particle
hit, as well as the ﬁt function to reconstruct the waveform, are p r ese nted.
Fig. 3. Single pixel waveform reconstructed by a ﬁt of the function f(t).
During the analysis, a threshold is applied on s in gl e pixel level. Since this t h re sh -
old is lower than the seed threshold during data taking, it is referred to as the
neighbour threshold. Adjacent pixe ls with a signal larger than the neighbour
threshold are combined to a clu st e r; and the position is reconstructed by linear
charge interpolati on and -correction. The distan ce be tween the predicted track
position on the Investigator and the reconstructed hit position is require d to be
within 100 µm. Moreove r, tracks passing through the outer half of the edge pixels
are discarded to avoid e.g. eects from the ﬁnite track prediction resolution .

3
4 Test-beam results
To explore the charge collection of the modiﬁed proc es s in detail, results are
projected onto the predic ted track position within individual pixel cells (in-pixel
presentation). A uniform eciency distribution c an be observed within the pixel
cell (see Figure 4). Fi gur e 5 shows the mean cluster size, deﬁned as the number of
pixels i n a cluster above threshold. As expected from geometrical considerations,
the lowest cluster size is obser ved in the pixel centre. The charge is shared most
likely to one n ei ghb ou r at the pixel edges, and to more than one neighbour at
the pixel corners. As shown in Figure 6, the impact of charge s hari n g is al so
reﬂected in the distribution of the high es t pixel signal (seed signal) in a cluster:
the more charge is share d between the pixels, the lower the se ed signal.
Fig. 4. Eciency within
the pixel cell.
Fig. 5. Mean cluster size
within the pixel cell.
Fig. 6. Mean seed signal
within the pixel cell.
A global eciency higher than 99 % and a spatial and timing resolution w it h
respect to the reference tracks of 6 µm and 5 ns, respectively, have been
measured. Even though the measur ed timing resolution is limited by the ADC
sampling frequency and the rise time of the output buer, the results are well
within the requirements for the CLIC tracker. In a next phase of R&D the results
on the Investigator test chip will be used to optimise the pixel layout for a fully
integrated chip for the CLIC tracker.
5 Simulation
A simulation chain using GEANT4 [11] to model the energy deposit in the sensor,
a 2-dimen si onal Technology Computer Aided Design (TCAD) [12] simulation to
model the devic e and perform a transient simulation of the charge collection,
and a parametric model to simulate energy ﬂuctuations and to perfor m the
position reconstruction has been developed [13]. The elect r ost at i c potential from
the TCAD simulation is shown in Fi gur e 7 and 8, respectively for the standard
and modiﬁed process. As indicated by the white lines, the depletion for the
standard process does extend over the full lateral size of the pixel, whereas the
expected full lateral depletion can be observed for the modiﬁed process. Results
are compared between simulation and data in Figure 9 - 11.

4
Fig. 7. Electrostatic potential from
Fig. 8. Electrostatic potential from
TCAD for the mo d i ed process.
A comparison of the mean cluster size in the X-direction within the pixel cell is
presented for t he standard process in Figure 9, showing a trend of larger cluster
sizes at the borders of the pixel at 0 and 1 in data, which is well de sc ri bed by
the simulation. For the modiﬁed process, an excellent agreement can be observed
between simulation and d at a in the residual distribution in Figur e 10, as well
as in the resolution, deﬁned as the Root Mean Square (RMS) of the residual
distribution, for dierent neighbour thresholds in Figure 11.
Fig. 9. Xclustersizewithin-
pixel cell standard process.
Fig. 10. Spatial residual
modiﬁed process.
Fig. 11. Spatial resid-
ual modiﬁed process.
6 Summary
The ALICE HR CMOS Investigator test chip has been explored in detail by
in-pixel t es t beam studies and a simulation based on GEANT4 and TCAD.
The simulation results reproduce the te st beam measurements, showing a good
understanding of the technology. An eciency of > 99 % and a spatial and
timing resolution of 6 µm and 5 ns, respectively, have been measured, using a
mini-matrix with a pitch of 28 µm and a bias voltage of 6 V. The measured
performance indic at es the suitability of the technology for the CLIC tracker and
the presented studies are used in a next R&D phase as input for the design of a
fully integrated chip for the CLIC tracker.

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### "Integrated CMOS sensor technologies..." refers methods in this paper

• ...The ALICE HR CMOS Investigator test chip has been explored in detail by in-pixel test beam studies and a simulation based on GEANT4 and TCAD....

[...]

• ...A simulation chain using GEANT4 [11] to model the energy deposit in the sensor, a 2-dimensional Technology Computer Aided Design (TCAD) [12] simulation to model the device and perform a transient simulation of the charge collection, and a parametric model to simulate energy fluctuations and to perform the position reconstruction has been developed [13]....

[...]

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• ...1 Introduction The Compact Linear Collider (CLIC) is an option for a future linear e+e collider at CERN in the post LHC era, reaching a centre of mass energy up to 3TeV [1, 2, 3, 4]....

[...]

• ...To suppress beam induced background particles, a time stamping accuracy of ⇠ 10 ns is required for the main tracker [2, 5]....

[...]

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12 Aug 2016
Abstract: The Compact Linear Collider (CLIC) is a multi-TeV high-luminosity linear e+e- collider under development. For an optimal exploitation of its physics potential, CLIC is foreseen to be built and operated in a staged approach with three centre-of-mass energy stages ranging from a few hundred GeV up to 3 TeV. The first stage will focus on precision Standard Model physics, in particular Higgs and top-quark measurements. Subsequent stages will focus on measurements of rare Higgs processes, as well as searches for new physics processes and precision measurements of new states, e.g. states previously discovered at LHC or at CLIC itself. In the 2012 CLIC Conceptual Design Report, a fully optimised 3 TeV collider was presented, while the proposed lower energy stages were not studied to the same level of detail. This report presents an updated baseline staging scenario for CLIC. The scenario is the result of a comprehensive study addressing the performance, cost and power of the CLIC accelerator complex as a function of centre-of-mass energy and it targets optimal physics output based on the current physics landscape. The optimised staging scenario foresees three main centre-of-mass energy stages at 380 GeV, 1.5 TeV and 3 TeV for a full CLIC programme spanning 22 years. For the first stage, an alternative to the CLIC drive beam scheme is presented in which the main linac power is produced using X-band klystrons.

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