scispace - formally typeset
Search or ask a question
Book Chapter•DOI•

Integrated CMOS sensor technologies for the CLIC tracker

R.M. Münker1, R.M. Münker2•
CERN1, University of Bonn2
27 Jun 2017-Vol. 213, pp 361-365
TL;DR: CMOS circuitry on a high resistivity epitaxial layer has been studied using the ALICE Investigator test-chip and a Technology Computer Aided Design based simulation chain has been developed to further explore the sensor technology.
Abstract: Integrated technologies are attractive candidates for an all silicon tracker at the proposed future multi-TeV linear \(\mathrm {e^{+} e^{-}}\) collider CLIC. In this context CMOS circuitry on a high resistivity epitaxial layer has been studied using the ALICE Investigator test-chip. Test-beam campaigns have been performed to study the Investigator performance and a Technology Computer Aided Design based simulation chain has been developed to further explore the sensor technology.

Summary (2 min read)

Jump to: [1 Introduction] – [2 The Investigator chip] – [3 Test beam data taking and reconstruction] – [4 Test-beam results] – [5 Simulation] and [6 Summary]

1 Introduction

  • To perform highly precise physics measurements, a single point resolution of 7µm and a material budget of 1 2%X0 per layer need to be reached in the large area tracker detector.
  • Integrated technologies are promising candidates in view of large-scale production and low material budget.
  • Test beam campaigns to study the Investigator High Resistivity (HR) CMOS test chip have been performed at the CERN SPS with a 120GeV pion beam.
  • As a reference system, the CLICdp Timepix3 telescope has been used, providing an excellent tracking and timing resolution on the Device Under Test (DUT) plane of ⇠ 2µm and 1 ns, respectively [6].

2 The Investigator chip

  • Within the ALICE ITS upgrade project, a fully monolithic chip, the ALPIDE [7], has been developed in a 180 nm High Resistivity (HR) CMOS process .
  • Using the same process, the Investigator test-chip has been developed [8, 9].
  • Various pixel layouts are implemented in di↵erent mini-matrices with 8 ⇥ 8 pixels, to study the impact of the pixel layout on the performance.
  • The standard process has been modified, inserting an additional n-layer to create a deep planar pn-junction and achieve full lateral depletion of the sensor.
  • The output bu↵ers are read out by external ADCs, sampling the individual pixel response with a frequency of 65MHz [9].

3 Test beam data taking and reconstruction

  • During the analysis, a threshold is applied on single pixel level.
  • Since this threshold is lower than the seed threshold during data taking, it is referred to as the neighbour threshold.
  • Adjacent pixels with a signal larger than the neighbour threshold are combined to a cluster; and the position is reconstructed by linear charge interpolation and ⌘-correction.
  • The distance between the predicted track position on the Investigator and the reconstructed hit position is required to be within 100µm.
  • Moreover, tracks passing through the outer half of the edge pixels are discarded to avoid e.g. e↵ects from the finite track prediction resolution.

4 Test-beam results

  • To explore the charge collection of the modified process in detail, results are projected onto the predicted track position within individual pixel cells (in-pixel presentation).
  • Figure 5 shows the mean cluster size, defined as the number of pixels in a cluster above threshold.
  • The charge is shared most likely to one neighbour at the pixel edges, and to more than one neighbour at the pixel corners.
  • A global e ciency higher than 99% and a spatial and timing resolution with respect to the reference tracks of ⇠ 6µm and ⇠ 5 ns, respectively, have been measured.
  • Even though the measured timing resolution is limited by the ADC sampling frequency and the rise time of the output bu↵er, the results are well within the requirements for the CLIC tracker.

5 Simulation

  • A simulation chain using GEANT4 [11] to model the energy deposit in the sensor, a 2-dimensional Technology Computer Aided Design (TCAD) [12] simulation to model the device and perform a transient simulation of the charge collection, and a parametric model to simulate energy fluctuations and to perform the position reconstruction has been developed [13].
  • The electrostatic potential from the TCAD simulation is shown in Figure 7 and 8, respectively for the standard and modified process.
  • As indicated by the white lines, the depletion for the standard process does extend over the full lateral size of the pixel, whereas the expected full lateral depletion can be observed for the modified process.
  • Results are compared between simulation and data in Figure 9 - 11.
  • For the modified process, an excellent agreement can be observed between simulation and data in the residual distribution in Figure 10, as well as in the resolution, defined as the Root Mean Square (RMS) of the residual distribution, for di↵erent neighbour thresholds in Figure 11.

6 Summary

  • The ALICE HR CMOS Investigator test chip has been explored in detail by in-pixel test beam studies and a simulation based on GEANT4 and TCAD.
  • The simulation results reproduce the test beam measurements, showing a good understanding of the technology.
  • The measured performance indicates the suitability of the technology for the CLIC tracker and the presented studies are used in a next R&D phase as input for the design of a fully integrated chip for the CLIC tracker.

Did you find this useful? Give us your feedback

Figures (10)

Content maybe subject to copyright    Report

CLICdp-Conf-2017-011
27 June 2017
Integrated CMOS sensor technologies for the CLIC tracker
M. Munker
1)⇤ †
On behalf of the CLICdp collaboration
⇤
CERN, Switzerland,
†
University of Bonn, Germany
Abstract
Integrated technologies are attractive candidates for an all silicon tracker at the proposed
future multi-TeV linear e
+
e
collider CLIC. In this context CMOS circuitry on a high res-
istivity epitaxial layer has been studied using the ALICE Investigator test-chip. Test-beam
campaigns have been performed to study the Investigator performance and a Technology
Computer Aided Design based simulation chain has been developed to further explore the
sensor technology.
Talk presented at International Conference on Technology and Instrumentation in Particle Physics 2017
(TIPP2017), Beijing, China, 22-26 May 2017
c
2017 CERN for the benefit of the CLICdp Collaboration.
Reproduction of this article or parts of it is allowed as specified in the CC-BY-4.0 license.
1
magdalena.munker@cern.ch
INTEGRATED CMOS SENSOR
TECHNOLOGIES FOR THE CLIC TRACKER
Magdalena Munker on behalf of the CLICdp collaboration
1
CERN magdalena.munker@cern.ch
2
University of Bonn
Abstract. Integrated technologies are attractive candidates for an all
silicon tracker at the proposed future multi-TeV linear e
+
e
collider
CLIC. In t h is context CMOS circuitry on a high resistivity epitaxial
layer has been studied using the ALICE Investigator test-chip. Test-beam
campaigns have been performed to stu d y the Investigator pe rform a n c e
and a Technology Computer Aided Design based simulation chain has
been developed to further explore the sensor technology.
1 Introduction
The Compact Linear Colli de r (CLIC) is an option for a future linear e
+
e
col-
lider at CERN in the post LHC era, reaching a centre of mass energy up to 3 TeV
[1, 2, 3, 4]. To perform highly precise physics measurements, a single point reso-
lution of 7 µm and a material budget of 1 2%X
0
per layer n ee d to be reached
in the large ar ea tracker detector. To suppress be am induced background par t i -
cles, a time stamping accuracy of ⇠ 10 ns is required for the main tracker [2, 5].
A large surface (⇠ 100 m
2
) all-silicon tracker is planned to address these require-
ments. Integrated technologies are promising candidates in view of large-scale
production and low material budget. Test beam campaigns to study the Investi-
gator High Resistivity (HR) CMOS test chip have been performed at the CERN
SPS with a 120 GeV pion beam. As a reference system, the CLICdp Timepix3
telescope has been used, providing an excellent tracking and timing resolution
on the Device Under Test (DUT) plane of ⇠ 2 µm and 1 ns, respectively [6].
2 The Investigator chip
Within the ALICE ITS upgrade project, a fully monolithic chip, the ALPIDE
[7], has been developed in a 180 nm High Resistivity (HR) CMOS process (see
Figure 1). Using the same process, the Investigator test-chip has been developed
[8, 9]. Various pixel layouts are implemented in di↵erent mini-matrices with
8 ⇥ 8 pixels, to study the impact of the pixel layout on the performance. The
standard p r ocess h as been modified, inserting an additional n-layer (see Figure
2) to create a deep planar pn-ju nc ti on and achieve full lateral depletion of the
sensor. The output of the source foll ower of each individual pixel is connected
to a dedicated output bu↵er with a rise time of ⇠ 10 ns.
2
P
-
P
++
backside
Deep.P-well
N-well
P-MOS
N-MOS
Fig. 1. Investiga to r standard
process schematic cross section.
N
-
P
Deep'P-well
N-well
P-MOS
N-MOS
Fig. 2. Investigator modified
process schematic cross section.
The outpu t bu↵ers are read out by external ADCs, sampling the individual
pixel response with a f r eq ue nc y of 65 MHz [9]. The presented studies have been
performed for a mini -m at ri x with a pixel pitch of 28 µm and a bias voltage of
6 V, using chips with an epitaxial layer thickness of 18 µm for the standard, and
25 µm for the modified process.
3 Test beam data taking and reconstruction
If at least one pixel crosses a seed threshold, the ful l analogue waveform of all
8 ⇥ 8 pix el s is read out. In Figure 3, a typical waveform of a pixel with a particle
hit, as well as the fit function to reconstruct the waveform, are p r ese nted.
Fig. 3. Single pixel waveform reconstructed by a fit of the function f(t).
During the analysis, a threshold is applied on s in gl e pixel level. Since this t h re sh -
old is lower than the seed threshold during data taking, it is referred to as the
neighbour threshold. Adjacent pixe ls with a signal larger than the neighbour
threshold are combined to a clu st e r; and the position is reconstructed by linear
charge interpolati on and ⌘-correction. The distan ce be tween the predicted track
position on the Investigator and the reconstructed hit position is require d to be
within 100 µm. Moreove r, tracks passing through the outer half of the edge pixels
are discarded to avoid e.g. e↵ects from the finite track prediction resolution .
3
4 Test-beam results
To explore the charge collection of the modified proc es s in detail, results are
projected onto the predic ted track position within individual pixel cells (in-pixel
presentation). A uniform efficiency distribution c an be observed within the pixel
cell (see Figure 4). Fi gur e 5 shows the mean cluster size, defined as the number of
pixels i n a cluster above threshold. As expected from geometrical considerations,
the lowest cluster size is obser ved in the pixel centre. The charge is shared most
likely to one n ei ghb ou r at the pixel edges, and to more than one neighbour at
the pixel corners. As shown in Figure 6, the impact of charge s hari n g is al so
reflected in the distribution of the high es t pixel signal (seed signal) in a cluster:
the more charge is share d between the pixels, the lower the se ed signal.
Fig. 4. Efficiency within
the pixel cell.
Fig. 5. Mean cluster size
within the pixel cell.
Fig. 6. Mean seed signal
within the pixel cell.
A global efficiency higher than 99 % and a spatial and timing resolution w it h
respect to the reference tracks of ⇠ 6 µm and ⇠ 5 ns, respectively, have been
measured. Even though the measur ed timing resolution is limited by the ADC
sampling frequency and the rise time of the output bu↵er, the results are well
within the requirements for the CLIC tracker. In a next phase of R&D the results
on the Investigator test chip will be used to optimise the pixel layout for a fully
integrated chip for the CLIC tracker.
5 Simulation
A simulation chain using GEANT4 [11] to model the energy deposit in the sensor,
a 2-dimen si onal Technology Computer Aided Design (TCAD) [12] simulation to
model the devic e and perform a transient simulation of the charge collection,
and a parametric model to simulate energy fluctuations and to perfor m the
position reconstruction has been developed [13]. The elect r ost at i c potential from
the TCAD simulation is shown in Fi gur e 7 and 8, respectively for the standard
and modified process. As indicated by the white lines, the depletion for the
standard process does extend over the full lateral size of the pixel, whereas the
expected full lateral depletion can be observed for the modified process. Results
are compared between simulation and data in Figure 9 - 11.
4
Fig. 7. Electrostatic potential from
TCAD for the standard process.
Fig. 8. Electrostatic potential from
TCAD for the mo d i fi ed process.
A comparison of the mean cluster size in the X-direction within the pixel cell is
presented for t he standard process in Figure 9, showing a trend of larger cluster
sizes at the borders of the pixel at 0 and 1 in data, which is well de sc ri bed by
the simulation. For the modified process, an excellent agreement can be observed
between simulation and d at a in the residual distribution in Figur e 10, as well
as in the resolution, defined as the Root Mean Square (RMS) of the residual
distribution, for di↵erent neighbour thresholds in Figure 11.
Fig. 9. Xclustersizewithin-
pixel cell standard process.
Fig. 10. Spatial residual
modified process.
Fig. 11. Spatial resid-
ual modified process.
6 Summary
The ALICE HR CMOS Investigator test chip has been explored in detail by
in-pixel t es t beam studies and a simulation based on GEANT4 and TCAD.
The simulation results reproduce the te st beam measurements, showing a good
understanding of the technology. An efficiency of > 99 % and a spatial and
timing resolution of 6 µm and 5 ns, respectively, have been measured, using a
mini-matrix with a pitch of 28 µm and a bias voltage of 6 V. The measured
performance indic at es the suitability of the technology for the CLIC tracker and
the presented studies are used in a next R&D phase as input for the design of a
fully integrated chip for the CLIC tracker.
Citations
More filters
Book Chapter•DOI•
A Vertex and Tracking Detector System for CLIC

[...]

Andreas Nürnberg1•
CERN1
28 Jun 2017
TL;DR: A detector concept meeting the requirements of the proposed future CLIC high-energy linear Open image in new window collider has been developed and an integrated R&D program addressing the challenges is progressing in the areas of ultra-thin sensors and readout ASICs, interconnect technology, mechanical integration and cooling.
Abstract: The physics aims at the proposed future CLIC high-energy linear Open image in new window collider pose challenging demands on the performance of the detector system. In particular the vertex and tracking detectors have to combine precision measurements with robustness against the expected high rates of beam-induced backgrounds. The requirements include ultra-low mass, facilitated by power pulsing and air cooling in the vertex-detector region, small cell sizes and precision hit timing at the few-ns level. A detector concept meeting these requirements has been developed and an integrated R&D program addressing the challenges is progressing in the areas of ultra-thin sensors and readout ASICs, interconnect technology, mechanical integration and cooling.
References
More filters
Dissertation•DOI•
Test-beam measurements and simulation studies of thin pixel sensors for the CLIC vertex detector

[...]

Niloufar Alipour Tehrani
21 Jun 2017
TL;DR: In this paper, a digitiser for AllPix, a Geant4-based simulation framework, has been developed in order to gain a deeper understanding of the charge deposition spectrum and the charge sharing in such thin sensors.
Abstract: The multiTeV e+e− Compact Linear Collider (CLIC) is one of the options for a future high-energy collider for the post-LHC era. It would allow for searches of new physics and simultaneously offer the possibility for precision measurements of standard model processes. The physics goals and experimental conditions at CLIC set high precision requirements on the vertex detector made of pixel detectors: a high pointing resolution of 3μm, very low mass of 0.2% X0 per layer, 10 ns time stamping capability and low power dissipation of 50 mW/cm2 compatible with air-flow cooling. In this thesis, hybrid assemblies with thin active-edge planar sensors are characterised through calibrations, laboratory and test-beam measurements. Prototypes containing 50μm to 150μm thin planar silicon sensors bump-bonded to Timepix3 readout ASICs with 55μm pitch are characterised in test beams at the CERN SPS in view of their detection efficiency and single-point resolution. A digitiser for AllPix, a Geant4-based simulation framework, has been developed in order to gain a deeper understanding of the charge deposition spectrum and the charge sharing in such thin sensors. The AllPix framework is also used to simulate the beam telescope and extract its tracking resolution. It is also employed to predict the resolution that can be achieved with future assemblies with thin sensors and smaller pitch. For CLIC, a full coverage of the vertex detector is essential while keeping the material content as low as possible. Seamless tiling of sensors, without the need for overlaps, by the active-edge technology allows for extending the detection capability to the physical edge of the sensor and thereby minimising the inactive regions. Thin-sensor prototypes containing active edges with different configurations are characterised in test-beams in view of the detection performance at the sensor edge. Technology Computer-Aided Design (TCAD) finiteelement simulations are implemented to reproduce the fabrication and the operation of such devices. The simulation results are compared to data for different edge terminations.

27 citations

"Integrated CMOS sensor technologies..." refers methods in this paper

  • ...As a reference system, the CLICdp Timepix3 telescope has been used, providing an excellent tracking and timing resolution on the Device Under Test (DUT) plane of ⇠ 2μm and 1 ns, respectively [6]....

    [...]

Requirements for the CLIC tracker readout

[...]

Andreas Nürnberg, Dominik Dannheim
25 Apr 2017
TL;DR: Nurnberg et al. as discussed by the authors proposed a multi-layer tracking detector system arranged in a barrel and endcap geometry with a total surface of approximately 100 m. This work was carried out in the framework of the CLICdp collaboration.
Abstract: The requirement of precision physics and the environment found in the proposed future high-energy linear e+e− collider CLIC result in challenging constraints for the silicon tracking detector. A track-momentum resolution of approximately σpT/p 2 T = 2×10 −5 GeV−1 for high-momentum tracks has to be achieved in an environment with high rates of beaminduced background events. The current layout foresees a multi-layer tracking detector system arranged in a barrel and endcap geometry with a total surface of approximately 100 m. This note describes the specifications for the tracker sensors and readout electronics. This work was carried out in the framework of the CLICdp collaboration andreas.nurnberg@cern.ch

16 citations

Journal Article•DOI•
Silicon pixel R&D for CLIC

[...]

M. Munker1•
CERN1
31 Jan 2017-Journal of Instrumentation
TL;DR: In this article, a wide range of sensor and readout ASIC technologies are investigated within the Compact Linear Collider (CLIC) silicon pixel R&D effort, including thin (50 μm-500 μm) slim edge and active-edge planar, and High-Voltage CMOS sensors hybridised to various readout ICs (Timepix, Timepix3, CLICpix) are presented.
Abstract: Challenging detector requirements are imposed by the physics goals at the future multi-TeV e+ e− Compact Linear Collider (CLIC). A single point resolution of 3 μm for the vertex detector and 7 μm for the tracker is required. Moreover, the CLIC vertex detector and tracker need to be extremely light weighted with a material budget of 0.2% X0 per layer in the vertex detector and 1–2% X0 in the tracker. A fast time slicing of 10 ns is further required to suppress background from beam-beam interactions. A wide range of sensor and readout ASIC technologies are investigated within the CLIC silicon pixel R&D effort. Various hybrid planar sensor assemblies with a pixel size of 25×25 μm2 and 55×55 μm2 have been produced and characterised by laboratory measurements and during test-beam campaigns. Experimental and simulation results for thin (50 μm–500 μm) slim edge and active-edge planar, and High-Voltage CMOS sensors hybridised to various readout ASICs (Timepix, Timepix3, CLICpix) are presented.

4 citations

Related Papers (5)
Development of high-performance monolithic CMOS detectors for space applications

[...]

01 Nov 2002
Franck Larnaudie, Bruno Vignon, Olivier Saint-Pé, Michel Tulet, Robert Davancens, Pierre Magnan, Philippe Martin-Gonthier, Franck Corbière, Stéphanie Basolo 
High-resolution CMOS particle detectors: design and test issues

[...]

01 Jan 2003
Daniele Passeri, Pisana Placidi, Leonardo Verducci, Paolo Ciampolini, Guido Matrella, Alessandro Marras, Gian Mario Bilei 
Advanced active pixel architectures in standard CMOS technology

[...]

05 Dec 2005-IEEE Transactions on Nuclear Science
Alessandro Marras, Daniele Passeri, G. Matrella, Pisana Placidi, M. Petasecca, L. Servoli, G. M. Bilei, P. Ciampolini 
Data acquisition board with optical gigabit interface

[...]

04 Jun 2005
J.E. DeGroaf, D. Herman, I.V. Kotova, M. A. Lisa, K. Ryan, F. S. Bieser 
Architecture of a Slow-Control ASIC for Future High-Energy Physics Experiments at SLHC

[...]

16 Jun 2009-IEEE Transactions on Nuclear Science
Alessandro Gabrielli, G. De Robertis, D. Fiore, F. Loddo, A. Ranieri 
Frequently Asked Questions (12)
Q1. What are the contributions mentioned in the paper "Integrated cmos sensor technologies for the clic tracker" ?

In this context CMOS circuitry on a high resistivity epitaxial layer has been studied using the ALICE Investigator test-chip. Reproduction of this article or parts of it is allowed as specified in the CC-BY-4. 0 license. In this context CMOS circuitry on a high resistivity epitaxial layer has been studied using the ALICE Investigator test-chip. In this context CMOS circuitry on a high resistivity epitaxial layer has been studied using the ALICE Investigator test-chip. Test-beam campaigns have been performed to study the Investigator performance and a Technology Computer Aided Design based simulation chain has been developed to further explore the sensor technology. Test-beam campaigns have been performed to study the Investigator performance and a Technology Computer Aided Design based simulation chain has been developed to further explore the sensor technology. Test-beam campaigns have been performed to study the Investigator performance and a Technology Computer Aided Design based simulation chain has been developed to further explore the sensor technology. 

Test beam campaigns to study the Investigator High Resistivity (HR) CMOS test chip have been performed at the CERN SPS with a 120GeV pion beam. 

Adjacent pixels with a signal larger than the neighbour threshold are combined to a cluster; and the position is reconstructed by linear charge interpolation and ⌘-correction. 

To perform highly precise physics measurements, a single point resolution of 7µm and a material budget of 1 2%X0 per layer need to be reached in the large area tracker detector. 

An e ciency of > 99% and a spatial and timing resolution of 6µm and 5 ns, respectively, have been measured, using a mini-matrix with a pitch of 28µm and a bias voltage of 6V. 

In a next phase of R&D the results on the Investigator test chip will be used to optimise the pixel layout for a fully integrated chip for the CLIC tracker. 

A simulation chain using GEANT4 [11] to model the energy deposit in the sensor, a 2-dimensional Technology Computer Aided Design (TCAD) [12] simulation to model the device and perform a transient simulation of the charge collection, and a parametric model to simulate energy fluctuations and to perform the position reconstruction has been developed [13]. 

As shown in Figure 6, the impact of charge sharing is also reflected in the distribution of the highest pixel signal (seed signal) in a cluster: the more charge is shared between the pixels, the lower the seed signal. 

The output of the source follower of each individual pixel is connected to a dedicated output bu↵er with a rise time of ⇠ 10 ns.2 P-P++ backsideDeep P-wellN-well P-MOSN-MOSFig. 

The distance between the predicted track position on the Investigator and the reconstructed hit position is required to be within 100µm. 

As indicated by the white lines, the depletion for the standard process does extend over the full lateral size of the pixel, whereas the expected full lateral depletion can be observed for the modified process. 

Even though the measured timing resolution is limited by the ADC sampling frequency and the rise time of the output bu↵er, the results are well within the requirements for the CLIC tracker.