Journal ArticleDOI
Integrating HDL synthesis and partitioning for multi-FPGA designs
Wen-Jong Fang,A.C.-H. Wu +1 more
Reads0
Chats0
TLDR
It is demonstrated that an integrated synthesis and partitioning methodology is crucial to achieving high-density designs with varying structural characteristics and HDL coding styles.Abstract:
The authors examine the interaction of HDL synthesis and multi-FPGA partitioning on designs with varying structural characteristics and HDL coding styles They demonstrate that an integrated synthesis and partitioning methodology is crucial to achieving high-density designsread more
Citations
More filters
Journal ArticleDOI
An Introduction to Reconfigurable Systems
TL;DR: This paper considers the generalization of reconfigurable systems as an important evolving discipline, bolstered by real-world archetypes such as field programmable gate arrays and software-definable radio (platform and application, respectively).
Journal ArticleDOI
Partitioning of Behavioral Descriptions with Exploiting Function-Level Parallelism
TL;DR: Experimental results demonstrate that this method leads to a shift of the explorable design space so that superior solutions which could not be explored by earlier work are included, showing the effectiveness of the proposed method.
Proceedings ArticleDOI
A technique for dynamic high-level exploration during behavioral-partitioning for multi-device architectures
TL;DR: A novel technique to perform dynamic high-level exploration of a behavioral specification that is being partitioned for a multi-device architecture that effectively satisfies the global latency constraint on the entire design, as well as the area constraints on the individual partition segments.
Book ChapterDOI
Automated design synthesis and partitioning for adaptive reconfigurable hardware
Ranga Vemuri,Sriram Govindarajan,Iyad Ouaiss,Meenakshi Kaul,Vinoo Srinivasan,Shankar Radhakrishnan,Sujatha Sundaraman,Satish Ganesan,Awartika Pandey,Preetham Lakshmikanthan +9 more
TL;DR: This chapter provides a description of a collection of synthesis and partitioning techniques and their embodiment in the SPARCS (Synthesis and Partitioning for Adaptive Reconfigurable Computing Systems) system.
Proceedings ArticleDOI
SOM on multi-FPGA ISA board-hardware aspects
D. Suzuki,O. Hammami +1 more
TL;DR: The hardware design of a multi-FPGA hardware implementation of a 16 neurons Self-Organizing Map (SOM) artificial neural network that outperforms under some conditions several software simulations implementations running on various PC hardware.
References
More filters
Proceedings ArticleDOI
A Linear-Time Heuristic for Improving Network Partitions
TL;DR: An iterative mincut heuristic for partitioning networks is presented whose worst case computation time, per pass, grows linearly with the size of the network.
Book
High ― Level Synthesis: Introduction to Chip and System Design
TL;DR: This paper presents a methodology for High-Level Synthesis of Architectural Models in Synthesis and its applications in Design Description Languages and Design Representation and Transformations.
Journal ArticleDOI
Recent directions in netlist partitioning: a survey
TL;DR: This survey describes research directions in netlist partitioning during the past two decades in terms of both problem formulations and solution approaches, and discusses methods which combine clustering with existing algorithms (e.g., two-phase partitioning).
Proceedings ArticleDOI
Circuit Partitioning for Huge Logic Emulation Systems
TL;DR: Given a huge system represented at gate level, an algorithm mapping the design into the minimum number of FPGAs for logic emulation is proposed, and a Set Covering partitioning approach is proposed to replace the widely adopted recursive partitioning paradigm.
Book
Digital Design Using Field Programmable Gate Arrays
Pak K. Chan,S. Mourad +1 more
TL;DR: The design of the FPGA was based on a model called Finite State Machine Design, which was derived from the model developed in the book “FPGA: Design of a Programming Environment, 2nd Ed.” (2003).
Related Papers (5)
A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations
Wen-Jong Fang,Allen C.-H. Wu +1 more