Integration of STT-MRAM model into CACTI simulator
Summary (3 min read)
Introduction
- Smullen et al. present a methodology and tool-chain for evaluating and comparing MTJs design [15].
- CACTI is a widely used high-level cache and memory modeling tool [9] [10].
- In order to prove the correctness of their tool, the authors generate STT-MRAM based cache memories with different sizes comparing the resulting performances with SRAM technology.
- An overview about STT-MRAM technology in terms of operation principles and electrical model is given.
A. Basic Principles
- STT-MRAM technology is built up upon the magnetic tunneling junction (MTJ) device which aims at persistently store logic data.
- Commonly, an MTJ device is composed of two ferromagnetic layers (FLs) interleaved with one oxide barrier layer.
- FLs are characterized by their magnetic orientation: one has a fixed magnetic orientation (fixed layer) and the other has a freely rotating magnetic orientation (free layer).
- By applying a sufficiently dense current pulse through the MTJ device, the free layer magnetic direction can be dynamically switched.
B. Electrical Model
- When the FLs exhibit the same magnetic orientation, the MTJ has a low electrical resistance, whereas MTJ experiences high electrical resistance in presence of antiparallel configuration.
- According to the relative magnetic orientations of the two layers, the electrical resistance of the MTJ is different.
- The most popular is the 1T-1MTJ whose structure is composed of one NMOS transistor and one MTJ device connected in series.
C. Writing Operation
- Many device-related parameters (e.g., MTJ area, material property) determine the write current amplitude that is required to change the free later magnetic direction.
- Moreover, it behaves differently according to the current pulse width.
- Based on the trade-off between write current amplitude and write pulse width, three distinct switching modes were identified [12]: thermal activation (TH), processional switching (PR), and dynamic reversal (DY) (Fig. 3).
- Looking at Figure 3, it is evident that when operating in processional switching zone small differences in write pulse width determine wide variation in current density.
- On the other hand, in the thermal activation area the required switching current increases very slowly even though the current pulse width is dramatically increased.
D. Reading Operation
- This current is, then, compared against a reference value (IREF) to discriminate the stored logic state.
- It is worth noticing here that both reading currents used to discriminate the logic state have the same order of magnitude.
- For this reason, a Sense Amplifier is commonly used to compare IR and IREF to determine the actual logic state of the cell.
- Different circuital schemas can be implemented to generate the reference current.
- One of the reference cells is in the parallel (low resistance) state while the other is in the antiparallel (high resistance) state.
E. Data Retention
- One of the most important parameter characterizing storage class memory devices is the amount of time the information is reliably stored into a cell.
- The data retention time of an STTMRAM bit-cell depends on thermal stability of the MTJ.
- It is usually evaluated by Equation (5): 𝑅G = 𝜏0𝑒H (5) The dependence of the retention time from Δ is exponential: the higher thermal stability, the longer retention time.
- Nevertheless, designing MTJ to increase the thermal stability corresponds to higher write energy.
F. CACTI
- CACTI is a widely used open-source high-level cache and memory modeling tool [13] [14] supported by HP Labs.
- CACTI models both traditional and non-uniform banked caches and memories using SRAM, and DRAM of which it can compute delay, power, and area.
- For a user-specified set of input parameters (e.g., energy/delay, memory size), the tool performs an exhaustive design space exploration across different array sizes and on-chip interconnections to identify, if existing, an optimal configuration that meets the input constraints.
- The authors research work aims at extending CACTI to support inplane STT-MRAM technology.
- By modeling bit-line, read circuitry, delay, area and energy consumption, additional parameters are combined with existing analytical models and seamless integrated with CACTI.
A. Array Modeling
- By integrating analytical models along with parameters extracted from ITRS roadmaps [17], CACTI supports modeling of array of targeted cache or memory devices.
- Each bank is composed of one or more subbanks which are comprised of identical mats.
- A Mat has 4 subarray which share pre-decoding logic and each subarray contain a set of wordlines and bitlines to access the basic memory cells.
- To support STT-MRAM technology, the authors mainly focus on mat and subarray.
C. Read Latency Model
- In order to estimate read latency the authors model both the bitline and the sense amplifier (SA).
- Nevertheless, CACTI currently has only models for voltage-base SA.
- The circuital schema involves two reference cells and three PMOS transistor to implement the current-to-voltage converter.
- Interested readers can refer to [16], for further details.
D. Write Latency Model
- The difference between read and write latency is quite relevant in STT-MRAM memories.
- Moreover, the required write voltage is between 1 and 2 volts whereas a smaller bias voltage (0.1V ~ 0.3V) is needed for reading.
- There exist a strong dependence between the write voltage and the expected write latency.
- Moreover, since CACTI does not provide a mechanism to input a distribution of desired logic values to be written, the authors only consider the switching case from parallel to anti-parallel magnetization of the free layer that is the worst case in terms of latency.
- But this contribution is not sufficient to estimate the overall latency as each STT-MRAM is connected to an access transistor to mitigate write disturbs and to reduce the energy consumption.
E. Area Estimation Model
- The area of STT-MRAM cell strongly depends on the design of the access transistor.
- Determining the proper size of the access transistor is one of the most critical aspects of the cell design.
- The analytical model integrated in CACTI for cell area estimation is given in the Equation (6).
- There is an inverse proportionality between them: a high resistance corresponds to a small cell area and high storage density, instead a low resistance increases considerably memory area.
- Interconnections considerably impact on resulting memory size, as well.
F. Energy Estimation Model
- For sake of completeness, the authors consider write and read energy model individually.
- A lower read voltage reduces the probability of read disturbs while a high value privileges read latency.
- The computation of write energy can be divided in two main contributions (see Equation (7)).
- (7) where Vwrite is the write voltage, RMTJ is the equivalent MTJ resistance, Racc is the equivalent NMOS resistance and τwrite is the MTJ switching time.
- In the previous section, the authors described modeling and integration of in-plane STT-MRAM technology into CACTI tool.
A. High-Performance Cache Memories
- For this study the authors generate high-performance, eight-way setassociative cache memories with no error correction mechanism which range in size from 32 kB to 512 kB.
- Transistors are modeled by resorting to high performance cells (itrs-hp) for both the data and tag array and peripheral circuit.
- Figure 4 (h) compares the read latency of the three different MTJ configurations with respect to SRAM.
- This is due to its small cell area given by the high resistance of the access transistor.
B. Low-Power Cache Memories
- Figure 4 (c) shows the read latency for low-power cache memories.
- The observed trend is quite similar to the one previously described in Figure (h).
- The motivation is that CACTI performs several optimizations, according to user constraints, that can change the internal partition of the array.
- The density improvements that STT-MRAM arrays can attain over SRAM arrays allow in-plane STT-MRAM to be a valid technology solution to design low-power cache memories compared to SRAM when read intensive applications are targeted , and Figure 4 (b)).
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Citations
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References
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"Integration of STT-MRAM model into ..." refers background or methods in this paper
...In [13] a pinned MTJ device is designed to have an electrical resistance equals to the average value of RL and RH....
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...CACTI is a widely used open-source high-level cache and memory modeling tool [13] [14] supported by HP Labs....
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195 citations
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...In this case, the resulting reference resistance is computed as the average between the low and high resistance values [14]....
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...CACTI is a widely used open-source high-level cache and memory modeling tool [13] [14] supported by HP Labs....
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131 citations
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...The key building block of STT-MRAM cell is the magnetic tunneling junction (MTJ) that is integrated with CMOS circuitry using 3-D technology [5]....
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...Such issues are mainly related to a) process variations of MOS and MTJ devices involving the variation of geometry size, threshold voltage, and magnetic materials [5], [6] b) the high write cost due to high switching current required to flip the MTJ state [7], , and c) the thermal fluctuations in the MTJ switching [8]....
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112 citations
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...Such issues are mainly related to a) process variations of MOS and MTJ devices involving the variation of geometry size, threshold voltage, and magnetic materials [5], [6] b) the high write cost due to high switching current required to flip the MTJ state [7], , and c) the thermal fluctuations in the MTJ switching [8]....
[...]
100 citations