Proceedings ArticleDOI
Intermediate fabrics: virtual architectures for circuit portability and fast placement and routing
James Coole,Greg Stitt +1 more
- pp 13-22
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TLDR
In this paper, a virtual reconfigurable architectures for different application domains, implemented on top of commercial off-the-shelf (COTS) devices, is proposed to hide the complexity of fine-grained physical devices and enable circuit portability across all devices that implement the intermediate fabric.Abstract:
Although hardware/software partitioning of embedded applications onto FPGAs is widely known to have performance and power advantages, FPGA usage has been typically limited to hardware experts, due largely to several problems: 1) difficulty of integrating hardware design tools into well-established software tool flows, 2) increasingly lengthy FPGA design iterations due to placement and routing, and 3) a lack of portability and interoperability resulting from device/platform-specific tools and bitfiles. In this paper, we directly address the last two problems by introducing intermediate fabrics, which are virtual reconfigurable architectures specialized for different application domains, implemented on top of commercial-off-the-shelf devices. Such specialization enables near-instantaneous placement and routing by hiding the complexity of fine-grained physical devices, while also enabling circuit portability across all devices that implement the intermediate fabric. When combined with existing work on runtime synthesis from software binaries, intermediate fabrics reduce the effects of all three problems by enabling transparent usage of COTS FPGAs by software designers. In this paper, we explore intermediate fabric architectures using specialization techniques to minimize area and performance overhead of the virtual fabric while maximizing routability and speedup of placement and routing. We present results showing an average placement and routing speedup of 554x, with an average area overhead of 10% and clock overhead of 18%, which corresponds to an average frequency of 195 MHz.read more
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Evolvable systems : from biology to hardware : 7th International Conference, ICES 2007, Wuhan, China, September 21-23, 2007 : proceedings
Lishan Kang,Yong Liu,Sanyou Zeng +2 more
TL;DR: Digital Hardware Evolution.
Proceedings ArticleDOI
HMFlow: Accelerating FPGA Compilation with Hard Macros for Rapid Prototyping
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Proceedings ArticleDOI
A Survey on FPGA Virtualization
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Proceedings ArticleDOI
FlexGrip: A soft GPGPU for FPGAs
TL;DR: The implementation of FlexGrip is described, a soft GPGPU architecture which has been optimized for FPGA implementation which supports direct CUDA compilation to a binary which is executable on the F PGPU without hardware recompilation.
Proceedings ArticleDOI
A high-performance overlay architecture for pipelined execution of data flow graphs
TL;DR: This work designs and evaluates an overlay architecture, structured as a mesh of functional units, for pipelined execution of data-flow graphs (DFGs), a common abstraction for expressing parallelism in applications, and designs a tool that maps DFGs to overlays.
References
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Book ChapterDOI
VPR: A new packing, placement and routing tool for FPGA research
Vaughn Betz,Jonathan Rose +1 more
TL;DR: In terms of minimizing routing area, VPR outperforms all published FPGA place and route tools to which the authors can compare and presents placement and routing results on a new set of circuits more typical of today's industrial designs.
Proceedings ArticleDOI
PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs
Larry E. McMurchie,Carl Ebeling +1 more
TL;DR: PathFinder as mentioned in this paper uses an iterative algorithm that converges to a solution in which all signals are routed while achieving close to the optimal performance allowed by the placement, which is achieved by forcing signals to negotiate for a resource and thereby determine which signal needs the resource most.
Book ChapterDOI
RaPiD - Reconfigurable Pipelined Datapath
TL;DR: RaPiD is presented, a new coarse-grained FPGA architecture that is optimized for highly repetitive, computation-intensive tasks that make much more efficient use of silicon than traditional FPGAs and also yield much higher performance for a wide range of applications.
Proceedings ArticleDOI
SPARK: a high-level synthesis framework for applying parallelizing compiler transformations
TL;DR: This paper presents a modular and extensible high-level synthesis research system that takes a behavioral description in ANSI-C as input and produces synthesizable register-transfer level VHDL, and shows how these transformations and other optimizing synthesis and compiler techniques are employed by a scheduling heuristic.
Journal ArticleDOI
The density advantage of configurable computing
TL;DR: The author attempts to answer questions as to why FPGAs have been so much more successful than their microprocessor and DSP counterparts and how configurable computing fits into the arsenal of structures used to build general, programmable computing platforms.