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Proceedings ArticleDOI

Internal monitoring of GBTx emulator using IPbus for CBM experiment

TL;DR: The Compressed Baryonic Matter (CBM) experiment is a part of the Facility for Antiproton and Ion Research (FAIR) in Darmstadt at GSI and a FPGA based Gigabit Transceiver (GBTx) emulator is implemented.
Abstract: The Compressed Baryonic Matter (CBM) experiment is a part of the Facility for Antiproton and Ion Research (FAIR) in Darmstadt at GSI. In CBM experiment a precisely time synchronized fault tolerant self-triggered electronics is required for Data Acquisition (DAQ) system in CBM experiments which can support high data rate (up to several TB/s). As a part of the implementation of the DAQ system of Muon Chamber (MUCH) which is one of the important detectors in CBM experiment, a FPGA based Gigabit Transceiver (GBTx) emulator is implemented. Readout chain for MUCH consists of XYTER chips (Front end electronics) which will be directly connected to detector, GBTx emulator, Data Processing Board (DPB) and First level event selector board (FLIB) with backend software interface. GBTx emulator will be connected with the XYTER emulator through LVDS (Low Voltage Differential Signalling) line in the front end and in the back end it is connected with DPB through 4.8 Gbps optical link. IPBus over Ethernet is used for internal monitoring of the registers within the GBTx. In IPbus implementation User Datagram Protocol (UDP) stack is used in transport layer of OSI model so that GBTx can be controlled remotely. A Python script is used at computer side to drive IPbus controller.
Citations
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Journal ArticleDOI
TL;DR: This paper presents the protocol design addressing the DAQ system requirements, simplifying the ASIC's back-end design and its adaptation for the STS and MUCH detector's conditions and a specific link synchronization technique, hit data bandwidth optimization and time synchronization method for the self-triggered front-end chip.
Abstract: The Silicon Tracking System, Muon Chamber, Transition Radiation Detector and Time-Of-Flight among others are the detector systems of the Compressed Baryonic Matter (CBM) experiment at the FAIR facility. These detector systems will be built with tens of thousands of front-end ASICs exposed to high radiation doses and difficult environmental and interference conditions. A CERN's GBTx-based solution was chosen for combining data from multiple front-end ASICs into an optical link before further concentration and preprocessing in the common Data Processing Board data hub. This paper presents the protocol design addressing the DAQ system requirements, simplifying the ASIC's back-end design and presents its adaptation for the STS and MUCH detector's conditions. A specific link synchronization technique, hit data bandwidth optimization and time synchronization method for the self-triggered front-end chip are presented.

22 citations

Journal ArticleDOI
TL;DR: A novel orthogonal concatenated code and cyclic redundancy check have been used to mitigate the effects of data corruption in the user data and a novel memory management algorithm is proposed that helps to process the data at the back-end computing nodes removing the added path delays.
Abstract: Due to the dramatic increase of data volume in modern high energy physics (HEP) experiments, a robust high-speed data acquisition (DAQ) system is very much needed to gather the data generated during different nuclear interactions. As the DAQ works under harsh radiation environment, there is a fair chance of data corruption due to various energetic particles like alpha, beta, or neutron. Hence, a major challenge in the development of DAQ in the HEP experiment is to establish an error resilient communication system between front-end sensors or detectors and back-end data processing computing nodes. Here, we have implemented the DAQ using field-programmable gate array (FPGA) due to some of its inherent advantages over the application-specific integrated circuit. A novel orthogonal concatenated code and cyclic redundancy check (CRC) have been used to mitigate the effects of data corruption in the user data. Scrubbing with a 32-b CRC has been used against error in the configuration memory of FPGA. Data from front-end sensors will reach to the back-end processing nodes through multiple stages that may add an uncertain amount of delay to the different data packets. We have also proposed a novel memory management algorithm that helps to process the data at the back-end computing nodes removing the added path delays. To the best of our knowledge, the proposed FPGA-based DAQ utilizing optical link with channel coding and efficient memory management modules can be considered as first of its kind. Performance estimation of the implemented DAQ system is done based on resource utilization, bit error rate, efficiency, and robustness to radiation.

4 citations


Cites methods from "Internal monitoring of GBTx emulato..."

  • ...controlling of FPGA devices, we have implemented IPbus protocol [20] over one gigabit Ethernet....

    [...]

Proceedings ArticleDOI
01 Oct 2016
TL;DR: In this article, an FPGA-based readout chain prototype comprising of an XYTER emulator, GBTx emulator, and DPB is developed where control and configuration signal of XYTER will be sent from DPB through GBTx simulator.
Abstract: The Compressed Baryonic Matter (CBM) experiment is a part of the Facility for Antiproton and Ion Research (FAIR) at Darmstadt, Germany. The challenge in CBM experiment is to measure the particles generated in nuclear collisions with unprecedented precision and statistics. To capture the data from each collision a highly time synchronized fault tolerant self-triggered electronics is required for Data Acquisition (DAQ) system that can support high data rate (up to several TB/s). Basic readout chain for CBM consists of a front-end Application Specific Integrated Circuit (ASIC) also known as X-Y Time Energy Read-out (XYTER) ASIC, a radiation hardened high speed optical transceiver board with Gigabit Transceiver (GBTx) ASIC followed by a Data Processing Board (DPB) and First Level Event Selector Interface Board (FLIB). As the first step towards the development of the readout chain, FPGA prototypes of GBTx ASIC and XYTER ASIC also known as GBTx emulator and XYTER emulator are developed. GBTx chips are connected to the XYTER in the front end through Low Voltage Differential Signalling (LVDS) electrical line also known as E-link and in the back-end with DPB using optical fiber. In this work, an FPGA-based readout chain prototype comprising of XYTER emulator, GBTx emulator, and DPB is developed where control and configuration signal of XYTER will be sent from DPB through GBTx emulator. A Python script is written in the computer to generate the control information that will be transferred to DPB through Ethernet using IPBus protocol.

3 citations


Cites methods from "Internal monitoring of GBTx emulato..."

  • ...A one Gbps custom Ethernet MAC is developed to use with IPbus [10]....

    [...]

Journal ArticleDOI
TL;DR: In this paper, the impact of large infrastructural experiments and possibilities they give to local, smaller but very active, university-based research groups and communities is discussed, and the background of the CBM detector infrastructure and electronic instrumentation just under design and test fabrication for this experiment is depicted.
Abstract: The research area of the compressed baryonic matter - CBM experiment (FAIR/GSI in Darmstadt) is sub-nuclear physics, thus hadron-baryon and quark-gluon, and the essence of phase transitions in the area of hot nuclear matter, and dense strongly interacting matter. Our interest in this paper are mainly considerations on the impact of such large infrastructural experiments and possibilities they give to local, smaller but very active, university based research groups and communities. Research and technical input from such groups is depicted on the background of the CBM detector infrastructure and electronic instrumentation just under design and test fabrication for this experiment. An essential input to this research originates from Poland via the agreed in-kind contribution. The areas of expertise of these groups are: superconductivity, structural large scale cabling, precision machined parts, RF and microwave technology, analog and advanced digital electronics, distributed measurement and control systems, etc .

3 citations

References
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BookDOI
TL;DR: The CBM Experiment as discussed by the authors has been used to study the properties of Strongly Interacting Matter (SIM) and its effects on collision dynamics and the CBM experiment in the real world.
Abstract: Part 0: General Introduction.- Part I: Bulk Properties of Strongly Interacting Matter.- Part II: In-Medium Excitations.- Part III Collision Dynamics.- Part IV: Observables and Predictions.- Part V The CBM Experiment.- Glossary.- References.

309 citations

Journal ArticleDOI
T. Uchida1
TL;DR: A TCP processor for Gigabit Ethernet with a circuit size suitable for implementing on a single Field Programmable Gate Array allows adoption of TCP/Ethernet in small devices that have hardware size limitations.
Abstract: Transmission control protocol (TCP) and Ethernet have been widely used in readout systems. These protocols are de facto standards and have been implemented on standard operating systems. However, some small devices, e.g., front-end devices and detectors, are not capable of employing these protocols because of hardware size limitations. This paper describes a TCP processor for gigabit Ethernet with a circuit size suitable for implementing on a single field programmable gate array. The only peripheral device required is a single Ethernet physical layer device. The hardware was implemented and its TCP throughput was measured. The throughputs in both directions simultaneously were at the upper limits of gigabit Ethernet. A mechanism for slow control over user datagram protocol (UDP) is also provided. The processor described here allows adoption of TCP/Ethernet in small devices that have hardware size limitations.

231 citations


"Internal monitoring of GBTx emulato..." refers methods in this paper

  • ...TCP is a connection oriented communication protocol with reliable data delivery, flow and congestion control and duplicate data suppression.(11) Another commonly used protocol in transport layer is User Datagram Protocol (UDP) which provides connectionless unreliable service....

    [...]

Proceedings ArticleDOI
01 Jan 2005
TL;DR: It is shown that the UDP/IP core area can be reduced to 1/3 of the original size with an appropriate implementation, accomplished by a trade-off between parallelism/latency and area.
Abstract: When designing FPGA-based Ethernet connected embedded systems the priority and necessity of requirements such as cost, area, flexibility etc. varies for each system. Simplified for most systems, it can be stated that no extra functionality than required is desired. Hence, when designing a UDP/IP stack in an FPGA a single UDP/IP stack "template" design is not suitable to effectively realize the different embedded network system requirements. We present three different UDP/IP stack cores, with different grades of parallelism and suited for various network demands. We show that the UDP/IP core area can be reduced to 1/3 of the original size with an appropriate implementation, accomplished by a trade-off between parallelism/latency and area. Furthermore guidelines are proposed on how to perform the trade-off between parallelism, area (cost), flexibility and functionality when designing an UDP/IP stack for compact embedded network systems.

51 citations

Journal ArticleDOI
TL;DR: This paper focuses on the interconnection network used as a part of the Data Acquisition System of the Compressed Baryonic Matter experiment at the Facility for Antiproton and Ion Research in Darmstadt, Germany.
Abstract: This paper focuses on the interconnection network used as a part of the Data Acquisition System of the Compressed Baryonic Matter experiment at the Facility for Antiproton and Ion Research in Darmstadt, Germany. This experiment will have special demands on the Data Acquisition System like limited space for hardware, radiation tolerance, flexibility for different types of network traffic and support for synchronization mechanisms. The specialty of the CBM network is that it uses only a single bidirectional fiber link for all network abilities and providing a deterministic latency message for precise time synchronisation. This led to the development of a new network and protocol.

25 citations


"Internal monitoring of GBTx emulato..." refers methods in this paper

  • ...1 CBMnet interface of nXYTER ASIC In the existing prototype nXYTER ASIC is connected with Readout Controller (ROC) board through Ethernet using CBM Network (CBMnet) Protocol .(5) ROC board sends the capture data from nXYTER to computer through ethernet....

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Proceedings ArticleDOI
25 Nov 2014
TL;DR: The evolution of the concepts leading from the functional requirements of the control and readout systems of the CBM experiment to the design of prototype implementation of the DPB boards are described and requirements on the board level and on the crate level are described.
Abstract: This paper presents a concept of the Data Processing Boards for the Compressed Baryonic Matter (CBM) experiment. Described is the evolution of the concepts leading from the functional requirements of the control and readout systems of the CBM experiment to the design of prototype implementation of the DPB boards. The paper describes requirements on the board level and on the crate level. Finally it discusses the prototype design prepared for testing and verification of proposed solutions, and selection of the final implementation.

19 citations

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