Investigation of Electrothermal Behaviors of 5-nm Bulk FinFET
TL;DR: In this article, the authors analyzed the localized thermal effect caused by self-heating effect (SE) in 5-nm bulk FinFETs that are scaled down, following the International Technology Roadmap for Semiconductors.
Abstract: The localized thermal effect caused by the self-heating effect (SE) becomes important for nanoscale 3-D transistors such as bulk FinFET because the thermal coupling from substrate is critical in such 3-D transistors. In this brief, we analyze the SE in 5-nm bulk FinFETs that are scaled down, following the International Technology Roadmap for Semiconductors. We systematically analyze the impact of key device parameters of bulk FinFET in view of the SE. Since the SE affects performance and reliability of transistors simultaneously, we define new figures of merit including ac delay and bias temperature instability for the first time, and it is found that the proper source/drain contact scheme design can achieve performance and reliability improvement at the same time in 5-nm bulk FinFET technology.
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TL;DR: In this paper, the self-heating effect in 14-nm bulk and SOI FinFETs is investigated through TCAD simulation, and several optimization thumbs of SHEs are proposed.
Abstract: In this paper, the self-heating effect (SHE) in 14-nm bulk and SOI FinFETs are investigated through the TCAD simulation. To achieve high authoritative evidences, the calibration is performed by ${I} _{\mathrm{ D}}$ - ${V} _{\mathrm{ G}}$ curve fitting based on the experimental data. The main contributions include: 1) The distribution of heat generation and temperature gradient along the channel are disclosed. Two peeks of heat generation are observed in source extension (SE) and drain extension (DE), respectively; 2) The dependence of maximum lattice temperature and thermal resistance on device geometry and parameters including fin width, fin height, length of SE and DE, the thickness of STI and BOX, doping concentration of extension, and gate voltage, are thoroughly analyzed; 3) The influence of SHEs on the electrical characteristic of FinFET under different ambient temperatures are also revealed. Moreover, the critical heat removal paths of bulk and SOI FinFETs are discussed. For the former, most of heat vertically diffuses to the substrate, and then to heat sink, whereas in SOI FinFET it firstly dissipates to source, drain, and gate, and then to heat sink. Finally, several optimization thumbs of SHEs are proposed.
20 citations
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...2964734 ON-current (Ion), transcondutance, and speed [4], [5]....
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TL;DR: In this paper, the authors report the thermal transport in sub 7-nm FinFETs technology based on phonon hydrodynamic equation (PHE), and highlight feasible strategies to enhance the heat ability, which can improve the thermal stability of the nanodevice.
Abstract: During the last ten years, the miniaturization of nanoscale field-effect transistors (FETs) predicted by Moore’s law has confronted an aggressive scaling down of the FET architecture (geometry and material) of nanoelectronics devices including phone mobile and computers. Built on thinner Fin body, FinFETs technologies are nonplanar devices based on scalable architecture suitable for the industry and nanomanufacturing methods. However, those emerging nanodevices suffer from thermal challenges related to self-heating effects and highest heat dissipation caused by thermal penetration. In this article, we report the nanoscale thermal transport in sub 7-nm FinFETs technology based on phonon hydrodynamic equation (PHE). Furthermore, we highlight feasible strategies to enhance the heat ability, which can improve the thermal stability of the nanodevice. This work presents a new physical picture of thermal performance optimizations in existing and future nanoelectronics devices.
14 citations
TL;DR: In this article, the Berkeley short-channel IGFET model-common multi-gate model is improved to account for the impact of substrate coupling on the RF parameters, and the model demonstrates excellent agreement with the measured data over a broad range of frequencies.
Abstract: The modeling of the advanced RF bulk FinFETs is presented in this letter. Extensive S-parameter measurements, performed on the advanced RF bulk FinFETs, show 31% improvement in cutoff frequency over recent work [1] . The transistor’s characteristics are dominated by substrate parasitics at intermediate frequencies (0.1–10 GHz) and gate parasitics at high frequencies (above 10 GHz). The Berkeley short-channel IGFET model-common multi gate model is improved to account for the impact of substrate coupling on the RF parameters. The model demonstrates excellent agreement with the measured data over a broad range of frequencies. The model passes AC, DC and RF symmetry tests, demonstrating its readiness for (RF) circuit design using FinFETs.
12 citations
Cites background from "Investigation of Electrothermal Beh..."
...[15] S. Makovejev, S. Olsen, and J. Raskin, “RF extraction of self-heating effects in FinFETs,” IEEE Trans....
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...The model has successfully passed all symmetry tests and shows excellent match with the measured data, proving its readiness for high-frequency circuit design using FinFETs....
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...However, this difference is very small in bulk FinFETs, as channel heat dissipates easily in bulk FinFETs [9] compared to FDSOI [10]–[14] or SOI FinFETs [15], [16]....
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...as channel heat dissipates easily in bulk FinFETs [9] compared to FDSOI [10]–[14] or SOI FinFETs [15], [16]....
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...[19] A. J. Scholten, G. D. J. Smit, R. M. T. Pijper, L. F. Tiemeijer, H. P. Tuinhout, J.-L. P. J. van der Steen, A. Mercha, M. Braccioli, and D. B. M. Klaassen, “Experimental assessment of self-heating in SOI FinFETs,” in IEDM Tech....
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TL;DR: In this paper, the authors used an electrothermal coupled Monte Carlo simulation framework to investigate the self-heating effect in 14 nm bulk nFinFETs with ambient temperature (TA) from 220 to 400 K.
Abstract: We use an electro-thermal coupled Monte Carlo simulation framework to investigate the self-heating effect (SHE) in 14 nm bulk nFinFETs with ambient temperature (TA) from 220 to 400 K. Based on this method, non-local heat generation can be achieved. Contact thermal resistances of Si/Metal and Si/SiO2 are selected to ensure that the source and drain heat dissipation paths are the first two heat dissipation paths. The results are listed below: (i) not all input power (Qinput) turns into heat generation in the device region and some is taken out by the thermal non-equilibrium carriers, owing to the serious non-equilibrium transport; (ii) a higher TA leads to a larger ratio of input power turning into heat generation in the device region at the same operating voltages; (iii) SHE can lead to serious degradation in the carrier transport, which will increase when TA increases; (iv) the current degradation can be 8.9% when Vds = 0.7 V, Vgs = 1 V and TA = 400 K; (v) device thermal resistance (Rth) increases with increasing of TA, which is seriously impacted by the non-equilibrium transport. Hence, the impact of TA should be carefully considered when investigating SHE in nanoscale devices.
8 citations
TL;DR: A new NBTI degradation model is proposed for FinFET devices that can be incorporated in Spice which allow to consider aging of a circuit in a design phase and results from the proposed model agree with Sentaurus degradation results.
Abstract: Aging is an important concern in long term reliability of semiconductor devices. In this regard, Bias Temperature Instability (BTI) is considered the major aging mechanism in nanometer regime, particularly in FinFET devices. Therefore, a well understanding of BTI mechanism in FinFET technology is of high interest. In this paper, a three-dimensional TCAD analysis about the impact of negative BTI (NBTI) FinFET technology is presented. In addition, a new NBTI degradation model is proposed for FinFET devices that can be incorporated in Spice which allow to consider aging of a circuit in a design phase. The three-dimensional TCAD analysis is performed using Synopsys Sentaurus tool. Results from the proposed model agree with Sentaurus degradation results.
7 citations
Cites methods from "Investigation of Electrothermal Beh..."
...Sentaurus is accurate tool that has been used to investigate reliability in FinFET and planar devices [14]....
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References
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12 Jun 2012
TL;DR: In this paper, a 22nm generation logic technology is described incorporating fully-depleted tri-gate transistors for the first time, which provides steep sub-threshold slopes (∼70mV/dec) and very low DIBL ( ∼50m V/V).
Abstract: A 22nm generation logic technology is described incorporating fully-depleted tri-gate transistors for the first time. These transistors feature a 3rd-generation high-k + metal-gate technology and a 5th generation of channel strain techniques resulting in the highest drive currents yet reported for NMOS and PMOS. The use of tri-gate transistors provides steep subthreshold slopes (∼70mV/dec) and very low DIBL (∼50mV/V). Self-aligned contacts are implemented to eliminate restrictive contact to gate registration requirements. Interconnects feature 9 metal layers with ultra-low-k dielectrics throughout the interconnect stack. High density MIM capacitors using a hafnium based high-k dielectric are provided. The technology is in high volume manufacturing.
705 citations
25 Sep 2006
TL;DR: Trends in transistor geometries and materials, from bulk silicon to carbon nanotubes, along with their implications for the thermal design of electronic systems are surveyed.
Abstract: As transistor gate lengths are scaled towards the 10-nm range, thermal device design is becoming an important part of microprocessor engineering. Decreasing dimensions lead to nanometer-scale hot spots in the transistor drain region, which may increase the drain series and source injection electrical resistances. Such trends are accelerated by the introduction of novel materials and nontraditional transistor geometries, including ultrathin body, FinFET, or nanowire devices, which impede heat conduction. Thermal analysis is complicated by subcontinuum phenomena including ballistic electron transport, which reshapes the heat generation region compared with classical diffusion theory predictions. Ballistic phonon transport from the hot spot and between material boundaries impedes conduction cooling. The increased surface to volume ratio of novel transistor designs also leads to a larger contribution from material boundary thermal resistance. This paper surveys trends in transistor geometries and materials, from bulk silicon to carbon nanotubes, along with their implications for the thermal design of electronic systems
573 citations
15 Oct 2012
TL;DR: At the 22-nm technology node, fully-depleted tri-gate transistors were introduced for the first time on a high-volume manufacturing process resulting in the highest drive currents yet reported for NMOS and PMOS.
Abstract: At the 22-nm technology node, fully-depleted tri-gate transistors were introduced for the first time on a high-volume manufacturing process Fabricated on a bulk silicon substrate, these transistors feature a third-generation high-k + metal-gate technology and a fifth generation of channel strain techniques resulting in the highest drive currents yet reported for NMOS and PMOS The use of tri-gate transistors provides steep subthreshold slopes (∼70 mV/decade) and very low DIBL (∼50 mV/V) values that are critical for low voltage operation Self-aligned contacts are implemented along with the tri-gate transistors to eliminate restrictive contact-to-gate registration requirements from scaling the gate pitch This enables an SRAM cell size of 0092 μm2 High yield and reliability have been demonstrated on multiple microprocessors
157 citations
"Investigation of Electrothermal Beh..." refers background or methods in this paper
...The device geometries correspond to 5-nm technology node whose values were estimated using 22-nm FinFET presented in [1] and [19] with the scaling factors of ITRS, [20], [21]....
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...BULK-FinFETs have newly emerged as a next level solution at the sub-22 nm technology node [1]....
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TL;DR: In this paper, the authors analyzed the self-heating effect in high-performance sub-0.18-/spl mu/m bulk and silicon-on-insulator (SOI) CMOS circuits using fast transient quasi-dc thermal simulations.
Abstract: As the technology feature size is reduced, the thermal management of high-performance very large scale integrations (VLSIs) becomes an important design issue. The self-heating effect and nonuniform power distribution in VLSIs lead to performance and long-term reliability degradation. In this paper, we analyze the self-heating effect in high-performance sub-0.18-/spl mu/m bulk and silicon-on-insulator (SOI) CMOS circuits using fast transient quasi-dc thermal simulations. The impact of the self-heating effect and technology scaling on the metallization lifetime and the gate oxide time-to-breakdown (TBD) reduction are also investigated. Based on simulation results, an optimized clock-driver design is proposed. The proposed layout reduces the hot-spot temperature by 15/spl deg/C and by 7/spl deg/C in 0.09-/spl mu/m SOI and bulk CMOS technologies, respectively.
157 citations
"Investigation of Electrothermal Beh..." refers background in this paper
...oxide and electromigration of the interconnect line [11]–[14]....
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TL;DR: In this paper, the authors developed algebraic expressions to account for the reduction in thermal conductivity due to the phonon boundary scattering for pure and doped silicon layers and presented the experimental data for 50-nm-thick single-crystal silicon layers at high temperatures.
Abstract: Simulations of the temperature field in silicon-on-insulator (SOI) and strained-Si transistors can benefit from experimental data and modeling of the thin silicon layer thermal conductivity at high temperatures. This paper develops algebraic expressions to account for the reduction in thermal conductivity due to the phonon-boundary scattering for pure and doped silicon layers and presents the experimental data for 50-nm-thick single-crystal silicon layers at high temperatures. The model applies to the temperature range of 300-1000 K for silicon layer thicknesses from 10 nm to 1 mum (and even bulk), which agrees well with the experimental data. In addition, the algebraic model has an excellent agreement with both the experimental data and predictions of thin-film thermal conductivity based on thermal conductivity integral and Boltzmann transport equation. The analytical thermal modeling and ISE-TCAD electrothermal simulations confirm that both the electrical and thermal performances of SOI transistor can be largely affected if the reduced thermal conductivity of the silicon due to phonon boundary scattering is not properly taken into consideration
120 citations
"Investigation of Electrothermal Beh..." refers methods in this paper
...In this brief, the electrical and thermal properties obtained from the previous experimental data, [15]–[18], are used in the calibration of Synopsys Sentaurus which is a commercial 3-D TCAD tool that solves drift-diffusion-based thermodynamics to simulate 5-nm bulk-FinFET....
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