Journal ArticleDOI
Investigation of Reliability Characteristics in NMOS and PMOS FinFETs
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TLDR
In this article, a three-dimensional vertical double-gate (FinFET) with a high aspect ratio (Si-fin height/width = Hfin/Wfin = 86 nm/17 nm) and a gate nitrided oxide of 14 Aring thickness has been successfully fabricated and reliability characterizations, including hot-carrier injection (HCI) and negative bias temperature instability (NBTI) for PMOS FinFETs, are carried out to determine their respective lifetimes.Abstract:
Three-dimensional vertical double-gate (FinFET) devices with a high aspect ratio (Si-fin height/width = Hfin/Wfin = 86 nm/17 nm) and a gate nitrided oxide of 14 Aring thickness have been successfully fabricated. Reliability characterizations, including hot-carrier injection (HCI) for NMOS FinFETs and negative bias temperature instability (NBTI) for PMOS FinFETs, are carried out in order to determine their respective lifetimes. The predicted HCI dc lifetime for a 50-nm gate-length NMOS FinFET device at the normal operating voltage (Vcc) of 1.1 V is 133 years. A wider fin-width (27 nm) PMOS FinFET exhibits promising NBTI lifetime such as 26.84 years operating at Vcc = 1.1 V, whereas lifetime is degraded for a narrower fin-width (17 nm) device that yields 2.76 years of lifetime at the same operating voltage and stress conditions.read more
Citations
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Proceedings ArticleDOI
A unified aging model of NBTI and HCI degradation towards lifetime reliability management for nanoscale MOSFET circuits
TL;DR: The model is based on the reaction-diffusion theory and extends it such that it covers the FinFET specific geometrical structures and it is computationally efficient, which makes it suitable for utilization in reliability-aware architectures as reliability prediction/assesment kernel for lifetime reliability management mechanisms.
Journal ArticleDOI
Effects of Fin Width on Device Performance and Reliability of Double-Gate n-Type FinFETs
Cheng-Li Lin,Po-Hsiu Hsiao,Wen-Kuan Yeh,Han-Wen Liu,Syuan-Ren Yang,Yu-Ting Chen,Kun-Ming Chen,Wen-Shiang Liao +7 more
TL;DR: In this paper, the impact of fin width (Wfins = 15, 20, and 25 nm) in a double-gate n-type FinFET on the performance and reliability of the device was investigated.
Proceedings ArticleDOI
Thermal behavior of self-heating effect in FinFET devices acting on back-end interconnects
TL;DR: This investigation shows the contribution of SH effect would change with varying joule heating, and it is important to considering the temperature rising from SH effect when assess the risk of back-end interconnects reliability.
Journal ArticleDOI
Reliability Modeling and Analysis of Hot-Carrier Degradation in Multiple-Fin SOI n-Channel FinFETs With Self-Heating
TL;DR: In this article, a comprehensive study on hot-carrier degradation mechanisms in 14 nm silicon-on-insulator (SOI) n-channel FinFETs is presented, where the impact of high-frequency AC stress bias on self-heating (SH) enhanced hotcarrier injection in oxide bulk traps is investigated and compared with the measurement results using the conventional DC stress bias.
Journal ArticleDOI
Effect of NBTI/PBTI aging and process variations on write failures in MOSFET and FinFET flip-flops
TL;DR: This work calculated and compared the effect of process variations and NBTI/PBTI aging on the Write Noise Margins of various MOSFET- and FinFet-based flip-flop cells and assessed a comparison for robustness among different circuit topologies and technologies.
References
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Intrinsic concentration, effective densities of states, and effective mass in silicon
TL;DR: In this paper, an inconsistency between commonly used values of the silicon intrinsic carrier concentration, the effective densities of states in the conduction and valence bands, and the silicon band gap is resolved by critically assessing the relevant literature.
Proceedings ArticleDOI
Sub-20 nm CMOS FinFET technologies
Yang-Kyu Choi,Nick Lindert,Peiqi Xuan,S. Tang,Daewon Ha,E. Anderson,T.-J. King,Jeffrey Bokor,Chenming Hu +8 more
TL;DR: In this paper, a simplified fabrication process for sub-20 nm CMOS double-gate FinFETs is reported, which is a more manufacturable process and has less overlap capacitance.
Journal ArticleDOI
Extension and source/drain design for high-performance FinFET devices
J. Kedzierski,Meikei Ieong,E.J. Nowak,Thomas S. Kanarsky,Ying Zhang,Ronnen Andrew Roy,Diane C. Boyd,David M. Fried,Hon-Sum Philip Wong +8 more
TL;DR: In this article, double gate devices based upon the FinFET architecture are fabricated, with gate lengths as small as 30 nm, with particular attention given to minimizing the parasitic series resistance.