scispace - formally typeset
Search or ask a question
Book ChapterDOI

Investigations on the Logic Circuit Behaviour of Hybrid CMOSFETs Comprising InGaAs nMOS and Ge pMOS Devices with Barrier Layers

01 Jan 2018-pp 149-160
TL;DR: In this paper, the authors investigated the logic circuit behavior of hybrid CMOS devices made of InGaAs n-channel and Ge p-channel MOSFETs with Si and InP barrier layers, respectively, at channel length L g = 20 and 30 nm.
Abstract: We investigate the logic circuit behaviour of hybrid CMOS devices made of InGaAs n-channel and Ge p-channel MOSFETs with Si and InP barrier layers, respectively, at channel length L g = 20 and 30 nm. Rise and fall time, noise margin of hybrid CMOS inverters and frequency of oscillations, energy-delay product of 3-stage ring oscillators comprising hybrid CMOS inverters have been investigated to evaluate the performance of the proposed CMOS device. Our findings show a significant amount of reduction of 92.2 and 82.5% for rise and fall time, respectively, in case of proposed hybrid inverter, compared with the corresponding values for equivalent Si CMOS at L g = 30 nm. Oscillation frequency of a 3-stage ring oscillator is found to be 264% higher when compared with its Si counterpart. Also there is an improvement of 17.8 and 77.4% in power-delay and energy-delay product, respectively, for hybrid CMOS inverters in comparison with their equivalent Si counterparts for a channel length of 30 nm. Similar trend is observed in case of channel length of 20 nm.
References
More filters
Journal ArticleDOI
TL;DR: In this paper, the effect of reduction of ultrathin TiO2 by Ti and its effect on Fermi level depinning and contact resistivity reduction to Si is experimentally studied.
Abstract: Experimental evidence of reduction of ultrathin TiO2 by Ti is presented and its effect on Fermi level depinning and contact resistivity reduction to Si is experimentally studied. A low effective barrier height of 0.15 V was measured with a Ti/10 A TiO2−x/n-Si MIS device, indicating 55% reduction compared to a metal/n-Si control contact. Ultra-low contact resistivity of 9.1 × 10−9 Ω-cm2 was obtained using Ti/10 A TiO2−x/n+ Si, which is a dramatic 13X reduction from conventional unannealed contacts on heavily doped Si. Transport through the MIS device incorporating the effect of barrier height reduction and insulator conductivity as a function of insulator thickness is comprehensively analyzed and correlated with change in contact resistivity. Low effective barrier height, high substrate doping, and high conductivity interfacial layer are identified as key requirements to obtain low contact resistivity using MIS contacts.

143 citations

Journal ArticleDOI
TL;DR: In this article, the most aggressive dimensions reported in Ge-channel transistors are pMOSFETs with 30-nm gate length on ultrathin germanium-on-insulator substrates (TGe = 25 nm).
Abstract: We present in this letter the most aggressive dimensions reported to date in Ge-channel transistors: pMOSFETs with 30-nm gate length on ultrathin germanium-on-insulator substrates (TGe = 25 nm). By improving both the Ge-enrichment technique and the transistor fabrication process, we demonstrate devices with controlled threshold voltage (Vth) and excellent short-channel effects. Moreover, the low defectivity and the very low thickness of the Ge film lead to a record drain OFF-state leakage for Ge-channel devices (< 1 nA/?m at VDS = -1 V) and thus, to the best ON-state to OFF-state current ratio (ION/IOFF ~5 × 105), even at Lg = 55 nm.

121 citations

Journal ArticleDOI
TL;DR: In this article, the dc behavior of single-gate and double-gate MOSFETs with gate lengths ranging from 5 to 100nm is simulated using drift-diffusion, hydrodynamic, and Monte Carlo approaches.

100 citations

Journal ArticleDOI
TL;DR: In this article, an analysis of junction leakage in heavily doped p+/n germanium junctions, targeted for short-channel transistor fabrication, is presented, where it is shown that the area-junction static power consumption for the best junctions remains below the power-density specifications for high performance applications.
Abstract: This paper presents an analysis of junction leakage in heavily doped p+/n germanium junctions, targeted for short-channel transistor fabrication There exists an optimal p+/n junction condition, with a doping concentration of 1 times 1017-5 times 1017 cm-3, where the area-leakage-current density is minimal Use of a halo-implant condition optimized for our 125-nm gate-length pMOS devices shows less than one decade higher area leakage than the optimal p+/n junction For even higher doping levels, the leakage density increases strongly Therefore, careful optimization of p+/n junctions is needed for decananometer germanium transistors The junction leakage shows good agreement with electrical simulations, although for some implant conditions, more adequate implant models are required Finally, it is shown that the area-junction static-power consumption for the best junctions remains below the power-density specifications for high-performance applications

69 citations

Journal ArticleDOI
TL;DR: In this article, scaled Ge p-channel FinFETs fabricated on a 300mm Si wafer using the aspect-ratio-trapping technique were reported. But, the performance of the Ge pFET was limited by the fact that the trap-assisted tunneling and a band-to-band tunneling leakage mechanism is responsible for an elevated bulk current limiting the OFF-state drain current.
Abstract: We report scaled Ge p-channel FinFETs fabricated on a 300-mm Si wafer using the aspect-ratio-trapping technique. For long-channel devices, a combination of a trap-assisted tunneling and a band-to-band tunneling leakage mechanism is responsible for an elevated bulk current limiting the OFF-state drain current. However, the latter can be mitigated by device design. We report low long-channel subthreshold swing of 76 mV/decade at VDS=-0.5 V, good short-channel effect control, and high transconductance (gm=1.2 mS/μm at VDS=-1 V and 1.05 mS/μm at VDS=-0.5 V for LG=70 nm). The Ge FinFET presented in this paper exhibits the highest gm/SSsat at VDD=1 V reported for nonplanar unstrained Ge p-FETs to date.

68 citations