Proceedings ArticleDOI
IO standard based energy efficient ALU design and implementation on 28nm FPGA
Bishwajeet Pandey,Jyotsana Yadav,Manisha Pattanaik +2 more
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TLDR
To achieve reduction in IOs power, this work is searching the most energy efficient LVCMOS(Low Voltage Complementary Metal Oxide Semiconductor) IO standard, whose power consumption is less in compare to other IO standard.Abstract:
In this work, target design is ALU. To achieve reduction in IOs power we are searching the most energy efficient LVCMOS(Low Voltage Complementary Metal Oxide Semiconductor) IO standard, whose power consumption is less in compare to other IO standard. There is 85.18% power reduction when we migrate from LVCMOS33 based ALU design to LVCMOS12 based ALU design. There is 41.45% power reduction when we migrate from LVCMOS33 based ALU design to LVCMOS25 based ALU design. Target FPGA family is 28nm Artix-7. Verilog is hardware description language used for design of ALU. There is 7.16% reduction in power for only LVCMOS15, when we change drive strength from 16 milliAmpere to 8 milli-Ampere. There is 5.44% reduction in power for LVCMOS18 when we change drive strength from 24 milliAmpere to 8 milli-Ampere. LVCMOS33 is the highest power consumer and LVCMOS12 is the lowest power consumer among the different available LVCMOS IO standard when there is common drive strength applied.read more
Citations
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Proceedings ArticleDOI
SSTL I/O Standard based environment friendly energyl efficient ROM design on FPGA
Meenakshi Bansal,Neha Bansal,Rishita Saini,Bishwajeet Pandey,Lakshay Kalra,D. M. Akbar Hussain +5 more
TL;DR: This work is operating ROM with the highest operating frequency of 4th generation i7 processor to test the compatibility of this design with the latest hardware in use, using Verilog hardware description language, Virtex-6 FPGA, and Xilinx ISE simulator.
Proceedings ArticleDOI
I/O standard based power optimized processor register design on ultra scale FPGA
TL;DR: This register is a building block of energy efficient processor based on LVCMOS (Low Voltage Complementary Metal Oxide I/O), HSTL(High Speed Transistor Logic), HSUL standard in FPGA and is implemented on 28nm 7 Series Kintex-7 (7k70tfbg676-3) FPGa.
Journal ArticleDOI
FPGA Based Low Power ROM Design Using Capacitance Scaling
Meenakshi Bansal,Neha Bansal,Rishita Saini,Lakshay Kalra,Preet Mohan Singh,Bishwajeet Pandey,D. M. Akbar Hussain +6 more
TL;DR: This work is going to design capacitance scaling based low power ROM design, and in order to test the compatibility of this ROM design with latest i7 Processor, it is operating this ROM with frequencies supported by i7 processor.
Journal ArticleDOI
Energy Efficient CRC Design for Processor of Workstation, and Server using LVCMOS
TL;DR: This work has designed CRC using the LVCMOS IO standards which are stands for Low Voltage Complementary Metal Oxide Semiconductor and the design is implemented on Virtex-6 FPGA family.
Book ChapterDOI
Input–Output Standard-Based Energy Efficient UART Design on 90 nm FPGA
TL;DR: It has been found out that LVCMOS18 consumes the least power and hence is the most efficient I/O standard for the UART design, thereby proving to be a boon in the field of electronics where power consumption is a major issue.
References
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Low-Power CMOS Synchronous Counter With Clock Gating Embedded Into Carry Propagation
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Proceedings ArticleDOI
Performance Analysis of 90nm Look Up Table (LUT) for Low Power Application
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Journal ArticleDOI
A Multidrop Bus Design Scheme With Resistor-Based Impedance Matching on Nonuniform Impedance Lines
Yohwan Yoon,Deog-Kyoon Jeong +1 more
TL;DR: In this paper, a bus design scheme that achieves both impedance matching and uniform power distribution for a multidrop bus is presented, and general formulas for determining the optimal line impedances and matching resistances are derived.