Irredundant binate realizations of unate functions
TL;DR: This paper exemplifies the fact that a circuit designer may construct many peculiar irredundant circuits realizing unate functions, and a counter-example is presented contradicting the existing notion of non-realizability of a unate function by a single-output, ir redundant, binate combinational circuit.
Abstract: Combinational circuits realizing unate Functions are usually simple in structure and their behaviour under the stuck-at fault model is seemingly well understood. This paper exemplifies the fact that a circuit designer may construct many peculiar irredundant circuits realizing unate functions. First, a counter-example is presented contradicting the existing notion of non-realizability of a unate function by a single-output, irredundant, binate combinational circuit. On the contrary, almost all unate functions are shown to be realizable with single-output networks that are binate as well as irredundant. A very rare example of a unate function is then cited; it has an irredundant circuit realization, none of whose primary input lines is unate.
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TL;DR: It is shown that even two-level irredundant circuits obtained by synthesis tools may admit isomorph-redundancy under multiple stuck-at faults, which reveals new insight and understanding of redundancy in sequential circuits.
Abstract: Design of irredundant and fully testable nonscan sequential circuits is a major concern of logic synthesis, as the presence of undetectable faults may render an ATPG intractable. This paper outlines some intriguing properties of isomorph faults, which are sequentially undetectable as well as redundant. An isomorph fault in a sequential circuit makes the state diagram of the faulty machine identical to that of the fault-free machine under certain renaming of states. Examples of reduced sequential machines whose circuit realization is combinationally irredundant, but isomorph-redundant, are hard to construct and very little is known about them. In this paper, many curious examples of such sequential circuits are presented wherein a single stuck-at fault causes isomorphic faulty machines. An infinite family of such circuits may, in fact, be constructed. It is shown that even two-level irredundant circuits obtained by synthesis tools may admit isomorph-redundancy under multiple stuck-at faults. Various classifications and related properties of isomorph faults are also reported. These results reveal new insight and understanding of redundancy in sequential circuits.
11 citations
Cites background from "Irredundant binate realizations of ..."
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12 May 2019
TL;DR: Pulsar, a method based on the extension of SDDS-NCL, a previously proposed asynchronous QDI template and design flow, is proposed, which can guarantee a maximum cycle time of 3.2ns, while the original Unclesynthesised circuit without logic optimisation leads to timing violations at a 6ns constraint.
Abstract: Asynchronous quasi-delay-insensitive (QDI) circuits are known for their potentially enhanced robustness to PVT variations when compared to synchronous circuits or to bundled data asynchronous design. They are also a good choice for high performance circuits used to solve several real-world problems. However, it is often difficult to constrain the minimum performance for QDI circuits. Thus, enhancing the synthesis quality for QDI design is a justifiable effort, especially in rising application fields, such as the Internet of Things and Artificial Intelligence. This work proposes Pulsar, a method based on the extension of SDDS-NCL, a previously proposed asynchronous QDI template and design flow. Pulsar brings four original contributions: (i) two new models for components used to as sequential barriers; (ii) a new model for half buffer pipelines, half-buffer channel network (HBCN); (iii) a linear programming formulation to define a circuit cycle time constraint; (iv) a design flow that enables automating the process to design sequential SDDS-NCL circuits. Experiments comparing synthesis results with Pulsar of a 6-stage, multiply-accumulate (MAC) show that it can guarantee a maximum cycle time of 3.2ns, while the original Unclesynthesised circuit without logic optimisation leads to timing violations at a 6ns constraint.
9 citations
Cites methods from "Irredundant binate realizations of ..."
...[16] it is possible that the synthesis tool to perform a binate realisation of a unate input function....
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Dissertation•
14 Jan 2016
TL;DR: O paradigma sincrono surge como uma alternativa, devido a sua robustez contra variacoes temporais e suporte ao projeto de circuitos de alto desepenho e baixo consumo, nosso mais novo template apresenta uma eficiencia energetica quase duas vezes maior.
Abstract: O paradigma sincrono foi, por decadas, a principal escolha da industria para o
projeto de circuitos integrados. Infelizmente, com o desenvolvimento da industria de semicondutores,
restricoes de projeto relativas a potencia de um circuito e incertezas de atrasos
aumentaram, dificultando o projeto sincrono. Alguns dos motivos para isso sao o aumento
na variabilidade dos processos de fabricacao de dispositivo, as perdas de desempenho relativas
em fios e as incertezas temporais causadas por variabilidades nas condicoes operacionais
de dispositivos. Dessa forma, o paradigma assincrono surge como uma alternativa,
devido a sua robustez contra variacoes temporais e suporte ao projeto de circuitos de alto
desepenho e baixo consumo. Entretanto, grande parte da industria de ferramentas de automacao
de projeto eletronico foi desenvolvida visando o projeto de circuitos sincronos e atualmente
o suporte a circuitos assincronos e consideravelmente limitado. Esta Tese propoe
novas tecnicas de projeto para otimizar circuitos assincronos, desde o nivel de celulas ao nivel
de sistema. Comecamos analisando e otimizando componentes basicos para o projeto
desses circuitos e depois apresentamos novas solucoes para implementa-los no nivel de
transistores. As otimizacoes propostas permitem uma melhor exploracao dos parâmetros
desses circuitos, incluindo potencia, atraso e area. Em um segundo momento, exploramos
o uso desses componentes como celulas para a geracao de uma biblioteca de suporte ao
projeto semi-dedicado de circuitos assincronos. Nesse contexto, propomos um fluxo completamente
automatizado para projetar tais bibliotecas. O fluxo compreende ferramentas
de dimensionamento de transistores e caracterizacao eletrica, desenvolvidas nesta Tese,
e uma ferramenta de projeto de leiaute, desenvolvida por um grupo de pesquisa parceiro.
Esse trabalho tambem apresenta uma biblioteca aberta, com centenas de componentes
validados extensivamente atraves de simulacoes pos-leiaute. Alem disso, usando essa biblioteca desenvolvemos novos templates para o projeto de circuitos assincronos no nivel
de sistema, propondo um fluxo automatico para sintese e mapeamento tecnologico. Comparado
a uma solucao assincrona no estado da arte, nosso mais novo template apresenta
uma eficiencia energetica quase duas vezes maior. As contribuicoes desta Tese permitiram
a construcao de uma infraestrutura para o projeto de circuitos assincronos, abrindo caminho
para a exploracao do uso de templates assincronos para solucionar problemas modernos e
futuros no projeto de circuitos integrados.
9 citations
28 Apr 1996
TL;DR: It is shown that an infinite family of such circuits can be constructed with isomorph-redundancy, and their properties reveal new insight and understanding of redundancy in sequential circuits.
Abstract: An isomorph fault in a sequential circuit makes the state diagram of the faulty machine identical to that of the fault-free machine, under the renaming of states. However, no example of a reduced sequential machine whose circuit realization is combinationally irredundant but isomorph-redundant, is yet known. This paper shows that an infinite family of such circuits can be constructed with isomorph-redundancy. Isomorph faults are then classified into various types. Their properties reveal new insight and understanding of redundancy in sequential circuits.
4 citations
References
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TL;DR: Failures, faults, and errors in digital systems are examined, and measures of dependability, which dictate and evaluate fault-tolerance strategies for different classes of applications, are defined.
Abstract: The basic concepts of fault-tolerant computing are reviewed, focusing on hardware. Failures, faults, and errors in digital systems are examined, and measures of dependability, which dictate and evaluate fault-tolerance strategies for different classes of applications, are defined. The elements of fault-tolerance strategies are identified, and various strategies are reviewed. They are: error detection, masking, and correction; error detection and correction codes; self-checking logic; module replication for error detection and masking; protocol and timing checks; fault containment; reconfiguration and repair; and system recovery. >
396 citations
TL;DR: It is shown that to detect t faults, t ≥ 1, in a network realizing an arbitrary n-variable logic function only tests need be applied ([x] is the integer part of x) and that these tests are independent of the function being realized.
Abstract: Fault detecting test sets to detect multiple stuck-at-faults (s-a-faults) in certain networks, realizing Reed-Muller(RM) canonic expressions called RM canonic (RMC) networks, are given. It is shown that to detect t faults, t ≥ 1, in a network realizing an arbitrary n-variable logic function only tests need be applied ([x] is the integer part of x) and that these tests are independent of the function being realized.
86 citations
TL;DR: It is proved that the set of minimal true vertices and maximal false vertices of the expanded truth table constitutes a test set to detect any number of stuck-at-faults in a network belonging to a class of restricted networks, called unate gate networks.
Abstract: The problem of designing fault detecting test sets from the functional description rather than the structural description of the networks realizing the logic function is studied. The concept of an expanded truth table for logic functions is introduced. It is proved that the set of minimal true vertices and maximal false vertices of the expanded truth table constitutes a test set to detect any number of stuck-at-faults in a network belonging to a class of restricted networks, called unate gate networks. It is further indicated that even in the presence of redundancies in the network, the test sets given remain valid.
76 citations
TL;DR: It is shown that, for AND/OR networks, universal test sets may be found that detect not only all single faults but all multiple faults as well.
Abstract: This paper examines the problem of finding a single universal test set that will test any of a variety of different implementations of a given switching function. It is shown that, for AND/OR networks, universal test sets may be found that detect not only all single faults but all multiple faults as well. The minimality and size of these sets are examined and their derivation for incomplete functions is described.
74 citations