IS-FPGA : a new symmetric FPGA architecture with implicit scan
30 Oct 2001-pp 924-931
TL;DR: It is demonstrated that the implicit-scan concept allows 'over-scan' of sequential circuits resulting in highly testable circuits and is transparent for the user as well as for the FPGA mapping tools.
Abstract: Proposes a new and original FPGA architecture with testability facilities. It is first demonstrated that classical FPGA architectures do not allow one to efficiently implement sequential circuits with a scan chain. It is consequently proposed to modify the architecture of classical FPGAs in order to create an implicit-scan chain into the FPGA itself called implicit scan FPGA (IS-FPGA). Using this new FPGA architecture, any sequential circuit implemented into the FPGA is 'implicitly scanned'. An original and optimal implementation of the proposed architecture is given with minimum area overhead and absolutely no delay impact. Additionally the technique is transparent for the user as well as for the FPGA mapping tools. Finally, it is demonstrated that the implicit-scan concept allows 'over-scan' of sequential circuits resulting in highly testable circuits.
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Book•
20 Nov 2007
TL;DR: This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and V LSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.
Abstract: Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost.
This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.
KEY FEATURES
* Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples.
* Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book.
* Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits.
* Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing.
* Practical problems at the end of each chapter for students.
151 citations
Book•
30 Jun 1992TL;DR: The introduction to FPGAs and a theoretical model for FPGA Routing, as well as some of the technologies used in that model, are described.
Abstract: Preface. Glossary. 1. Introduction to FPGAs. 2. Commercially Available FPGAs. 3. Technology Mapping for FPGAs. 4. Logic Block Architecture. 5. Routing for FPGAs. 6. Flexibility of FPGA Routing Architectures. 7. A Theoretical Model for FPGA Routing. References. Index.
129 citations
TL;DR: Testing techniques for interconnect and logic resources of an arbitrary design implemented into a field-programmable gate array (FPGA) are presented and this approach is able to achieve 100% fault coverage.
Abstract: Testing techniques for interconnect and logic resources of an arbitrary design implemented into a field-programmable gate array (FPGA) are presented. The target fault list includes all stuck-at, open, and pair-wise bridging faults in the mapped design. For interconnect testing, only the configuration of the used logic blocks is changed, and the structure of the design remains unchanged. For logic block testing, the configuration of used logic resources remains unchanged, while the interconnect configuration and unused logic resources are modified. Logic testing is performed in only one test configuration whereas interconnect testing is done in a logarithmic number of test configurations. This approach is able to achieve 100% fault coverage
59 citations
Cites methods from "IS-FPGA : a new symmetric FPGA arch..."
...Application-dependent testing of FPGAs has been addressed in [5], [16], [17], [24], and [25]....
[...]
...A new FPGA architecture with design for testability features is presented in [25]....
[...]
07 Oct 2002
TL;DR: An FPGA test and coverage methodology is presented and use of an "iterative logic unit" and its impact on test and fault grading is discussed.
Abstract: This paper presents an FPGA test and coverage methodology. BIST and "shift register" styles of test are discussed. Gate level fault grading results are then presented. Use of an "iterative logic unit" and its impact on test and fault grading is discussed.
48 citations
25 Apr 2004
TL;DR: An application-dependent test strategy to be used by an FPGA user is presented which requires only 3 test configurations and the used logic blocks are fully tested by modifying the interconnect configuration.
Abstract: An application-dependent test strategy to be used by an FPGA user is presented which requires only 3 test configurations. In this specific strategy, the interconnect is first tested by modifying the logic block configuration and preserving the interconnect configuration. Then, the used logic blocks are fully tested by modifying the interconnect configuration. Results for some benchmark applications mapped into the Xilinx FPGAs are also provided.
41 citations
Cites methods from "IS-FPGA : a new symmetric FPGA arch..."
...Previous work on application-dependent testing of FPGAs has been reported in [Das 99] [Krasniewski 96,97,99][Mitra 98] [Quddus 99][Renovell 01]....
[...]
References
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01 Jan 1994
TL;DR: The purpose of this chapter was to discuss the design and implementation of SRAM Programmable FPGAs, as well as some of the techniques used in the development of Erasable Programmable Logic Devices.
Abstract: Preface. 1: Introduction. 1.1. Logic Implementation Options. 1.2. What is an FPGA? 1.3. Advantages of FPGAs. 1.4. Disadvantages of FPGAs. 1.5. Technology Trends. 1.6. Designing for FPGAs. 1.7. Outline of Subsequent Chapters. 1.8. References. 2: SRAM Programmable FPGAs. 2.1. Introduction. 2.2. Programming Technology. 2.3. Device Architecture. 2.4. Software. 2.5. The Future. 2.6. Design Applications. 2.7. Acknowledgements 2.8. References. 3. Antifuse Programmed FPGAs. 3.1. Introduction. 3.2. Programming Technology. 3.3. Device Architecture. 3.4. Software. 3.5. The Future. 3.6. Design Applications. 3.7. Acknowledgements. 3.8. References. 4. Erasable Programmable Logic Devices. 4.1. Introduction. 4.2. Programming Technology. 4.3. Device Architecture. 4.4. Software. 4.5. The Future. 4.6. Design Applications. 4.7. References. Index.
345 citations
18 Oct 1998
TL;DR: The first BIST approach for testing the programmable routing network in FPGAs is introduced, which detects opens in, and shorts among, wiring segments, and also faults affecting theprogrammable switches that configure the FPGA interconnect.
Abstract: We introduce the first BIST approach for testing the programmable routing network in FPGAs. Our method detects opens in, and shorts among, wiring segments, and also faults affecting the programmable switches that configure the FPGA interconnect. As a result, the BIST technique provides complete testing of interconnect faults.
180 citations
Patent•
07 Oct 1998
TL;DR: In this paper, a threshold gate exhibits hysteresis such that the output remains ASSERTED while the number of ASSERTed inputs remains greater than zero and less than the threshold value.
Abstract: An array includes a set of cells (21, 23, 25, 27, 29, 31). At least one of which includes a threshold gate (33, 35) having a plurality of inputs, an output, and a threshold value. Signals may assume an ASSERTED state having a logic meaning and a NULL state that has no logic meaning. The gate output switches to NULL when all inputs are NULL, and switches to the ASSERTED state when the number of ASSERTED inputs exceeds the threshold value. In the preferred embodiment, the gate exhibits hysteresis such that the output remains ASSERTED while the number of ASSERTED inputs remains greater than zero and less than the threshold value. In an alternate embodiment, an array of simplified threshold elements is used to form more complex threshold gates.
155 citations
Book•
30 Jun 1992TL;DR: The introduction to FPGAs and a theoretical model for FPGA Routing, as well as some of the technologies used in that model, are described.
Abstract: Preface. Glossary. 1. Introduction to FPGAs. 2. Commercially Available FPGAs. 3. Technology Mapping for FPGAs. 4. Logic Block Architecture. 5. Routing for FPGAs. 6. Flexibility of FPGA Routing Architectures. 7. A Theoretical Model for FPGA Routing. References. Index.
129 citations
27 Apr 1997
TL;DR: A methodology for testing RAM-based FPGA taking into account the configurability of such flexible devices is proposed and it is demonstrated that a set of only 3 Test Configurations suffice to make 100% of the considered realistic fault set non-redundant.
Abstract: This paper proposes a methodology for testing RAM-based FPGA taking into account the configurability of such flexible devices. Two different approaches with different objectives are identified: the Manufacturing Test Procedure and the User Test Procedure. The proposed method is used to generate a Manufacturing Test Procedure targeting the Interconnect Structure of RAM-based FPGA. It is demonstrated that a set of only 3 Test Configurations called the Orthogonal, the Diagonal-1 and Diagonal-2 Test Configurations suffice to make 100% of the considered realistic fault set non-redundant. Then the test of each configuration is shown equivalent to the test of classical buses. The final proposed Manufacturing Test Procedure present a constant number of Test Configurations (3) and very short Test Sequences.
116 citations