Patent•
Isolation techniques for reducing dark current in CMOS image sensors
26 Aug 2004-
TL;DR: In this article, the authors provided a method and structure for isolating the regions of a semiconductor device by providing a trench in an active area of a substrate, growing an epitaxial layer in the trench to fill the trench or to partially fill the trenches, and depositing an insulating material over the epitaxia layer and within the trenches to complete the trench.
Abstract: Isolation methods and devices for isolating regions of a semiconductor device. The isolation method and structure include forming an isolating trench in an active area and filling the trench with a doped conductive material containing silicon. Suitable conductive materials containing silicon include polysilicon and silicon-germanium. There is also provided a method and structure for isolating the regions by providing a trench in an active area of a substrate, growing an epitaxial layer in the trench to fill the trench or to partially fill the trench and depositing an insulating material over the epitaxial layer and within the trench to completely fill the trench.
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Patent•
29 Jun 2007
TL;DR: In this article, the authors proposed a method for manufacturing a semiconductor device, in which the number of photolithography steps can be reduced, the manufacturing process can be simplified, and manufacturing can be performed with high yield at low cost.
Abstract: An object is to provide a method for manufacturing a semiconductor device, in which the number of photolithography steps can be reduced, the manufacturing process can be simplified, and manufacturing can be performed with high yield at low cost A method for manufacturing a semiconductor device includes the following steps: forming a semiconductor film; irradiating a laser beam by passing the laser beam through a photomask including a shield for shielding the laser beam; subliming a region which has been irradiated with the laser beam through a region in which the shield is not formed in the photomask in the semiconductor film; forming an island-shaped semiconductor film in such a way that a region which is not irradiated with the laser beam is not sublimed because it is a region in which the shield is formed in the photomask; forming a first electrode which is one of a source electrode and a drain electrode and a second electrode which is the other one of the source electrode and the drain electrode; forming a gate insulating film; and forming a gate electrode over the gate insulating film
323Â citations
Patent•
28 Dec 2005
TL;DR: In this article, a complementary metal-oxide semiconductor (CMOS) image sensor and a method for fabricating the same are disclosed, which includes a sub-layer having a photodiode and a plurality of transistors formed thereon, a pad insulating layer formed on the sublayer, a micro-lens forming on the pad, and a planarization layer forming a color filter.
Abstract: A complementary metal-oxide semiconductor (CMOS) image sensor and a method for fabricating the same are disclosed. The image sensor includes a sub-layer having a photodiode and a plurality of transistors formed thereon, a pad insulating layer formed on the sub-layer, a micro-lens formed on the pad insulating layer, the micro-lens including a first insulating layer having an uneven surface and a second insulating layer covering upper and side surfaces of a projected portion of the first insulating layer to form a dome shape, and a planarization layer formed on the micro-lens, and a color filter formed on the planarization layer.
132Â citations
Patent•
05 Nov 2008TL;DR: In this paper, a photoelectric conversion region and a charge storage region in a semiconductor layer are formed, and a transistor is formed on a front surface of the semiconductor layers.
Abstract: Provided are an image sensor and a method of manufacturing the same. The method may include forming a photo-electric conversion region and a charge storage region in a semiconductor layer; forming a transistor on a front surface of the semiconductor layer; forming a recess by etching a portion of the semiconductor layer between the charge storage region and a rear surface of the semiconductor layer; and forming on a bottom surface of the recess a shield film that blocks light incident on the charge storage region.
114Â citations
Patent•
13 Oct 2004
TL;DR: In this article, an improved image sensor includes an array of germanium photo-sensitive elements integrated with a silicon substrate and integrated with silicon readout circuits, which are then formed overlying the silicon by epitaxial growth.
Abstract: In accordance with the invention, an improved image sensor includes an array of germanium photosensitive elements integrated with a silicon substrate and integrated with silicon readout circuits. The silicon transistors are formed first on a silicon substrate, using well known silicon wafer fabrication techniques. The germanium elements are subsequently formed overlying the silicon by epitaxial growth. The germanium elements are advantageously grown within surface openings of a dielectric cladding. Wafer fabrication techniques are applied to the elements to form isolated germanium photodiodes. Since temperatures needed for germanium processing are lower than those for silicon processing, the formation of the germanium devices need not affect the previously formed silicon devices. Insulating and metallic layers are then deposited and patterned to interconnect the silicon devices and to connect the germanium devices to the silicon circuits. The germanium elements are thus integrated to the silicon by epitaxial growth and integrated to the silicon circuitry by common metal layers.
105Â citations
Patent•
27 Dec 2008
TL;DR: In this paper, a hybrid electric drive system for an automotive vehicle comprises a heat engine, an electric motor, a one-way-clutch, a torque-limiting clutch, and a transmission.
Abstract: A hybrid electric drive system for an automotive vehicle comprises a heat engine, an electric motor, a one-way-clutch, a torque-limiting clutch, and a transmission. The one-way-clutch disposed between the engine shaft and the motor shaft, and it can transmit torque from the engine shaft to the motor shaft. The transmission has an input shaft being connected to the motor shaft and an output shaft to drive the wheels. The torque-limiting clutch is also disposed between the engine shaft and the motor shaft. When it is disengaged, the torque-limiting clutch disconnects the motor shaft from the engine shaft, so the motor can solely drive the vehicle. When it is engaged, the clutch transmits a pre-determined level of torque from the motor shaft to the engine shaft in order to start the engine. The torque limiting clutch will smooth out the torque peak when the system starts the engine while the vehicle is running.
94Â citations
References
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TL;DR: In this paper, a 2.0 /spl mu/m double-poly, double-metal foundry CMOS active pixel image sensor is reported, which uses TTL compatible voltages, low noise and large dynamic range, and is useful in machine vision and smart sensor applications.
Abstract: A new CMOS active pixel image sensor is reported. The sensor uses a 2.0 /spl mu/m double-poly, double-metal foundry CMOS process and is realized as a 128/spl times/128 array of 40 /spl mu/m/spl times/40 /spl mu/m pixels. The sensor features TTL compatible voltages, low noise and large dynamic range, and will be useful in machine vision and smart sensor applications. >
302Â citations
08 Feb 1996
TL;DR: In this paper, an active pixel sensor (APS) is integrated on a CMOS chip with the timing and control circuits, and signal conditioning to enable random access, low power (/spl sim/5 mW) operation, and low read noise (13 e/sup -/ rms).
Abstract: A CMOS imaging sensor is described that uses active pixel sensor (APS) technology and permits the integration of the detector array with on-chip timing, control, and signal chain electronics. This sensor technology has been used to implement a CMOS APS camera-on-a-chip. The camera-on-a-chip features a 256/spl times/256 APS sensor integrated on a CMOS chip with the timing and control circuits, and signal-conditioning to enable random-access, low power (/spl sim/5 mW) operation, and low read noise (13 e/sup -/ rms). The chip features simple power supplies, fast readout rates, and a digital interface for commanding the sensor, as well as for programming the window-of-interest readout and exposure times. Excellent imaging has been demonstrated with the APS camera-on-a-chip, and the measured performance indicates that this technology will be competitive with charge-coupled devices (CCD's) in many applications.
256Â citations
Patent•
14 Jul 1999TL;DR: In this paper, a CMOS imager with an improved signal to noise ratio and improved dynamic range is described, which provides improved charge storage by fabricating a storage capacitor in parallel with the photocollection area of the imager.
Abstract: A CMOS imager having an improved signal to noise ratio and improved dynamic range is disclosed. The CMOS imager provides improved charge storage by fabricating a storage capacitor in parallel with the photocollection area of the imager. The storage capacitor may be a flat plate capacitor formed over the pixel, a stacked capacitor or a trench imager formed in the photosensor. The CMOS imager thus exhibits a better signal-to-noise ratio and improved dynamic range. Also disclosed are processes for forming the CMOS imager.
234Â citations
Patent•
IBM1
TL;DR: In this paper, a method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure was proposed, where a pad layer is formed on the silicon layer.
Abstract: A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon layer. The pad layer includes a pad nitride (e.g., silicon nitride) on a pad oxide (e.g., silicon dioxide), and the pad oxide has been formed on the silicon layer. A trench is formed by anisotropically etching through the pad layer, the silicon layer, the BOX, and to a depth within the bulk silicon substrate. Insulative spacers are formed on sidewalls of the trench. An epitaxial silicon layer is grown in the trench from a bottom of the trench to above the pad layer. The pad layer and portions of the epitaxial layer are removed (e.g., by chemical mechanical polishing), resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer. Electronic devices may be formed within the epitaxial silicon of the trench. Such electronic devices may include dynamic random access memory (DRAM), bipolar transistors, Complementary Metal Oxide Semiconductor (CMOS) circuits which are sensitive to floating body effects, and devices requiring threshold voltage matching. Semiconductor devices (e.g., field effect transistors) may be coupled to the SOI structure outside the trench.
119Â citations
Patent•
IBM1
TL;DR: The void-free pattern of isolation in a semiconductor substrate is described in this article, where a pattern of substantially vertically sided trenches is described, where the base or bottom of the trenches are open to the monocrystalline semiconductor body.
Abstract: The void-free pattern of isolation in a semiconductor substrate is described. There is contained within a semiconductor body a pattern of substantially vertically sided trenches. The pattern of isolation trenches isolate regions of monocrystalline semiconductor material which may contain active and passive semiconductor devices. The depth of the pattern of trenches is greater than about 3 micrometers. A first insulating layer is located upon the sidewalls of the trenches. The base or bottom of the trenches is open to the monocrystalline semiconductor body. An epitaxial layer extending from the base of the trenches fills the pattern of trenches up to between about 500 to 1500 nanometers from the upper surface of the trenches. A capping second insulating layer fills the additional portion of the pattern of trenches above the upper surfaces of the epitaxial layer for isolation of the pattern of trenches from the ambient. It is the dense epitaxial monocrystalline semiconductor which prevents the formation of voids within the pattern of trenches. The epitaxial layer must be grown in such a way so as no spurious growth occurs upon the principal surfaces of the substrate, because such growth would prevent the satisfactory chemical-mechanical polishing of the C.V.D. insulator layer.
108Â citations