Patent
JTAG interface system for communicating with compliant and non-compliant JTAG devices
Reads0
Chats0
TLDR
In this paper, the authors present a system and method for using standard JTAG protocol for testing protocol compliant and non-protocol compliant digital devices without altering the JTAG or the non-compliant device.Abstract:
A system and method for using standard JTAG protocol for testing protocol compliant and non-protocol compliant digital devices without altering the JTAG protocol or the non-compliant device. A specialized Test Access Port Controller controls and monitors the states applied to the non-compliant device in order to eliminate the PAUSE state in the non-compliant device and to limit the Run-Test/Idle state to one clock period.read more
Citations
More filters
Patent
System and method for communicating with an integrated circuit
TL;DR: In this paper, the authors present a system and method for communicating with an integrated circuit that allows the integrated circuit to communicate debugging information and system bus transaction information with an external system.
Patent
Microprocessor having improved memory management unit and cache memory
TL;DR: In this article, the permission for a memory access in a data processing system having a virtual cache memory and a translation look-aside buffer is discussed and a determination is made based on the logical address information of the memory access operation and the permission information associated with the access operation.
Patent
Selectively accessing test access ports in a multiple test access port environment
TL;DR: A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface as mentioned in this paper.
Patent
Apparatus and method for storing trace information
TL;DR: In this article, a non-intrusive trace system for processing trace information from one or more processors is presented. The trace system can be configured by a user to operate in various modes for flexibly storing or transmitting the trace information.
Patent
Led printhead and driver chip for use therewith having boundary scan test architecture
Michael John Donahue,Paul J Fleming,Fox Tracy,Edward Michael Kelly,Mattern Michael William,Carl Michael Petruzelli +5 more
TL;DR: In this article, a non-impact printhead with a plurality of driver IC chips and a number of recording elements such as LEDs is presented, where a test circuit interface is provided by a test access port for input of update command signals and clock inputs to the test circuit.
References
More filters
Patent
Emulation devices, systems and methods utilizing state machines
TL;DR: An emulation device including a serial scan testability interface having at least first and second scan paths, and state machine circuitry connected and responsive to said second scan path generally operable for emulation control of logical circuitry associated with said emulation device as discussed by the authors.
Patent
Architecture for system-wide standardized intra-module and inter-module fault testing
Joseph H. Brown,Dilip K. Bhavsar +1 more
TL;DR: In this article, the authors present an approach and method for hierarchical, centralized boundary-scan fault-testing of extended electronic circuits, including inter-board testing, within a unified, standard protocol.
Patent
Hierarchical connection method apparatus and protocol
TL;DR: In this article, a protocol and associated circuitry for efficiently extending serial bus capability into multi-level system environments is described, which enables the use of a common serial bus in a hierarchically arranged system or network, so that a primary serial bus master device can selectively access any device at any level or position in the network and send and receive messages and commands to and from the device.
Patent
Emulation devices, systems and methods with distributed control of test interfaces in clock domains
TL;DR: An emulation device distributes common control information (8801) to each of a plurality of clock domains (1213, 1215, 1217) into which the emulation device is partitioned, and also provides the clock domains with individualized clock control (8905, 8907, 8913).
Patent
Bussed test access port interface and method for testing and controlling system logic boards
TL;DR: In this article, a bussed TAP interface is incorporated into a system control interface for testing and controlling system logic boards in a manner that is fully compliant with the IEEE 1149.1 standard, while conserving system controller card signals.
Related Papers (5)
Architecture for system-wide standardized intra-module and inter-module fault testing
Joseph H. Brown,Dilip K. Bhavsar +1 more