Junctionless multigate field-effect transistor
TL;DR: In this article, the authors describe a metaloxide-semiconductor MOS transistor concept in which there are no junctions and the channel doping is equal in concentration and type to the source and drain extension doping.
Abstract: This paper describes a metal-oxide-semiconductor MOS transistor concept in which there are no junctions. The channel doping is equal in concentration and type to the source and drain extension doping. The proposed device is a thin and narrow multigate field-effect transistor, which can be fully depleted and turned off by the gate. Since this device has no junctions, it has simpler fabrication process, less variability, and better electrical properties than classical MOS devices with source and drain PN junctions.
Citations
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TL;DR: A new type of transistor in which there are no junctions and no doping concentration gradients is proposed and demonstrated, which has near-ideal subthreshold slope, extremely low leakage currents, and less degradation of mobility with gate voltage and temperature than classical transistors.
Abstract: All existing transistors are based on the use of semiconductor junctions formed by introducing dopant atoms into the semiconductor material. As the distance between junctions in modern devices drops below 10 nm, extraordinarily high doping concentration gradients become necessary. Because of the laws of diffusion and the statistical nature of the distribution of the doping atoms, such junctions represent an increasingly difficult challenge for the semiconductor industry. Here, we propose and demonstrate a new type of transistor in which there are no junctions and no doping concentration gradients. These devices have full CMOS functionality and are made using silicon nanowires. They have near-ideal subthreshold slope, extremely low leakage currents, and less degradation of mobility with gate voltage and temperature than classical transistors.
2,090 citations
01 Nov 2010
TL;DR: In this article, a junctionless nanowire transistors (gated resistors) are compared to inversion-mode and accumulation-mode MOS devices using bulk conduction instead of surface channel.
Abstract: Conduction mechanisms in junctionless nanowire transistors (gated resistors) are compared to inversion-mode and accumulation-mode MOS devices. The junctionless device uses bulk conduction instead of surface channel. The current drive is controlled by doping concentration and not by gate capacitance. The variation of threshold voltage with physical parameters and intrinsic device performance is analyzed. A scheme is proposed for the fabrication of the devices on bulk silicon.
458 citations
Patent•
19 Aug 2010
TL;DR: In this article, a system includes a semiconductor device consisting of a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single-crystalline silicon layer.
Abstract: A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.
417 citations
Patent•
28 Jun 2011
TL;DR: In this paper, a first layer and a second layer of layer-transferred mono-crystallized silicon, where the first layer comprises a first plurality of horizontally-oriented transistors, and the second layer includes a second plurality of vertically oriented transistors.
Abstract: A device comprising semiconductor memories, the device comprising: a first layer and a second layer of layer-transferred mono-crystallized silicon, wherein the first layer comprises a first plurality of horizontally-oriented transistors; wherein the second layer comprises a second plurality of horizontally-oriented transistors; and wherein the second plurality of horizontally-oriented transistors overlays the first plurality of horizontally-oriented transistors.
413 citations
TL;DR: In this paper, the temperature dependence of the main electrical parameters of junctionless (JL) silicon nanowire transistors is investigated and compared to the standard inversion-and accumulation-mode FETs.
Abstract: This paper investigates the temperature dependence of the main electrical parameters of junctionless (JL) silicon nanowire transistors. Direct comparison is made to silicon nanowire (trigate) MOSFETs. Variation of parameters such as threshold voltage and on-off current characteristics is analyzed. The JL silicon nanowire FET has a lager variation of threshold voltage with temperature than the standard inversion- and accumulation-mode FETs. Unlike in classical devices, the drain current of JL FETs increases when temperature is increased.
370 citations
References
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TL;DR: In this paper, a single doping impurity atom is introduced in the undoped channel region of the device and the resulting shift of threshold voltage is measured from the simulated I-V characteristics.
Abstract: In this paper, we investigate random doping fluctuation effects in trigate SOI MOSFETs by solving the three-dimensional (3D) Poisson, drift-diffusion and continuity equations numerically. A single doping impurity atom is introduced in the undoped channel region of the device and the resulting shift of threshold voltage is measured from the simulated I–V characteristics. This enables the derivation of the threshold voltage shift (DVTH) for any arbitrary location of the doping atom in the transistor. Based on an analysis of a sub-20 nm trigate MOSFET device, we find that the typical variation of VTH per doping atom is a few tens of mV. Inversion-mode (IM) trigate devices are more sensitive to the doping fluctuation effects than accumulation-mode (AM) devices. The threshold voltage shift arising from doping fluctuations is maximum when the doping atom is near the center of the channel region, which means the original SOI film doping, the random contamination effects or any other impurity doping in the channel region is more important than atoms introduced in the channel by the S/D implantation process for sub-20 nm transistors.
34 citations
TL;DR: In this paper, the authors investigated channel doping in fin-type double-gate (DG) MOSFETs and found that the threshold voltage was more sensitive to the dopants in the accumulation mode than in the inversion mode.
Abstract: We investigated channel doping in fin-type double-gate (DG) MOSFETs. We demonstrated through experiments that the threshold voltage was more sensitive to the dopants in the accumulation mode than in the inversion mode. We also found that significant deviation in the threshold voltage from the expected value arose in ultrathin fin-type DG MOSFETs. We attributed this phenomenon to the unexpected dopant loss from the ultrathin channels due to segregation. This finding means that careful doping adjustments must be made in ultrathin-channel devices.
32 citations
TL;DR: In this paper, the behavior of single and double gate accumulation mode SOI MOSFETs was investigated and it was shown that short channel effects such as DIBL and sub-threshold swing degradation are substantially reduced in the volume accumulation regime.
Abstract: The behavior of single and double gate accumulation mode silicon-on-insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs) is thoroughly investigated. Accumulation mode devices present advantages over inversion mode transistors regarding transconductance, ease of fabrication, and parasitic effects. We have concluded, from experimental results and 2D simulations, that short channel effects such as DIBL and subthreshold swing degradation are substantially reduced in the volume accumulation regime, being even lower in thin-film double gate accumulation mode SOI MOSFETs than in inversion mode double gate SOI devices for adequate technological characteristics. The potential of thin-film accumulation mode SOI MOS transistors down to sub-0.1 mum technologies and up to 125 degrees C is demonstrated. (C) 2001 The Electrochemical Society.
22 citations
TL;DR: In this article, the performances of accumulation-mode and inversion-mode multigate FETs are compared and the influence of gate underlap on the electrical properties is analyzed.
Abstract: The performances of accumulation-mode and inversion-mode multigate FETs are compared. The influence of gate underlap on the electrical properties is analyzed. Both simulation results and experimental data show that in a device with gate underlap, accumulation-mode devices have a higher current drive, lower source and drain resistance and less process variability than inversion-mode FETs.
18 citations
TL;DR: In this article, the electrical characteristics of multi-gate MOSFETs using the advanced radical gate oxide and a suppression of negative bias temperature degradation in accumulation mode FD-SOI MOSFLETs are described.
13 citations