Proceedings ArticleDOI
Karna: A Gate-Sizing based Security Aware EDA Flow for Improved Power Side-Channel Attack Protection
Patanjali Slpsk,Prasanna Karthik Vairam,Chester Rebeiro,V. Kamakoti +3 more
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TLDR
This work proposes an algorithm called Karna that can be incorporated in the Electronic Design Automation (EDA) flow, in order to significantly improve the side-channel security of the device, without impacting the other device characteristics.Abstract:
Power side-channel attacks pose a serious threat to the security of embedded devices. Most available countermeasures have significant overheads resulting in the application not meeting its requirements of low-power, high-performance and small area. We propose an algorithm called Karna11Karna, much like Achilles from Greek mythology, was born with a shield that protected him from attacks. Similarly, Our proposed scheme, Karna protects the design from power side-channel attacks in the manufacturing phase or in other words the chip is manufactured(born) with a shield. that can be incorporated in the Electronic Design Automation (EDA) flow, in order to significantly improve the side-channel security of the device, without impacting the other device characteristics. Karna does not add additional logic but rather achieves this by first identifying vulnerable gates in the design and then reconfiguring these gates to increase side-channel resistance. Unlike contemporary works, Karna does not require any specialized gate library but uses the gates available in the standard cell library. We integrate Karna into the Synopsys Design Compiler and demonstrate its efficacy at reducing side-channel leakage in implementations of AES, PRESENT and Simon block ciphers, synthesized for a 28nm technology node. An interesting observation is that Karna only uses the available space around the gates to perform this optimization and does not incur any additional area overheads. We showcase the side-channel resistance of these optimized designs using a Differential Power Analysis attack. Our proposed approach is able to reduce the power side-channel of the designs while incurring no penalty in delay, power and gate-count.read more
Citations
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Journal ArticleDOI
An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools
TL;DR: An overview of hardware security and trust from the perspectives of threats, countermeasures, and design tools is presented to motivate hardware designers and electronic design automation tool developers to consider the new challenges and opportunities of incorporating an additional dimension of security into robust hardware design, testing, and verification.
Posted Content
SoK: Design Tools for Side-Channel-Aware Implementations.
TL;DR: This SoK classify approaches to automated leakage detection based on the model's source of truth on two main parameters: whether the model includes measurements from a concrete device and the abstraction level of the device specification used for constructing the model.
Posted Content
Architecture Correlation Analysis (ACA): Identifying the Source of Side-channel Leakage at Gate-level.
TL;DR: The methodology, Architecture Correlation Analysis, uses a leakage model, well known from differential side-channel analysis techniques, to rank the cells within a netlist according to their contribution to the sidechannel leakage, and can selectively apply countermeasures where they are most effective.
Journal ArticleDOI
Power Side-Channel Leakage Assessment Framework at Register-Transfer Level
TL;DR: In this article , a register transfer level (RTL) power analysis tool (PAT) framework is presented to perform a technology-independent power side-channel (PSC) assessment of cryptographic hardware at the RTL stage.
Proceedings ArticleDOI
Architecture Correlation Analysis (ACA): Identifying the Source of Side-channel Leakage at Gate-level
TL;DR: In this article, the authors proposed a methodology to determine the source of side-channel leakage at the granularity of a single cell at the design time, at the gate-level within the AES module as well as within the overall SoC.
References
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Proceedings ArticleDOI
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Kris Tiri,Ingrid Verbauwhede +1 more
TL;DR: A novel design methodology to implement a secure DPA resistant crypto processor that combines standard building blocks to make 'new' compound standard cells, which have a close to constant power consumption.
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Proceedings Article
A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards
TL;DR: A set of logic gates and flip-flops needed for cryptographic functions and compared those to Static Complementary CMOS implementations to protect security devices such as smart cards against power attacks are built.