scispace - formally typeset
Search or ask a question
Journal ArticleDOI

Latchup-free ESD protection design with complementary substrate-triggered SCR devices

28 Jul 2003-IEEE Journal of Solid-state Circuits (Institute of Electrical and Electronics Engineers Inc.)-Vol. 38, Iss: 8, pp 1380-1392
TL;DR: In this article, latchup-free electrostatic discharge (ESD) protection circuits, which are combined with the substrate-triggered technique and an SCR device, are proposed.
Abstract: The turn-on mechanism of silicon-controlled rectifier (SCR) devices is essentially a current triggering event. While a current is applied to the base or substrate of an SCR device, it can be quickly triggered on into its latching state. In this paper, latchup-free electrostatic discharge (ESD) protection circuits, which are combined with the substrate-triggered technique and an SCR device, are proposed. A complementary circuit style with the substrate-triggered SCR device is designed to discharge both the pad-to-V/sub SS/ and pad-to-V/sub DD/ ESD stresses. The novel complementary substrate-triggered SCR devices have the advantages of controllable switching voltage, adjustable holding voltage, faster turn-on speed, and compatible to general CMOS process without extra process modification such as the silicide-blocking mask and ESD implantation. The total holding voltage of the substrate-triggered SCR device can be linearly increased by adding the stacked diode string to avoid the transient-induced latchup issue in the ESD protection circuits. The on-chip ESD protection circuits designed with the proposed complementary substrate-triggered SCR devices and stacked diode string for the input/output pad and power pad have been successfully verified in a 0.25-/spl mu/m salicided CMOS process with the human body model (machine model) ESD level of /spl sim/7.25 kV (500 V) in a small layout area.

Content maybe subject to copyright    Report

Citations
More filters
Journal ArticleDOI
TL;DR: An overview on the electrostatic discharge (ESD) protection circuits by using the silicon controlled rectifier (SCR)-based devices in CMOS ICs is presented and the solutions to overcome latchup issue in the SCR-based devices are discussed.
Abstract: An overview on the electrostatic discharge (ESD) protection circuits by using the silicon controlled rectifier (SCR)-based devices in CMOS ICs is presented The history and evolution of SCR device used for on-chip ESD protection is introduced Moreover, two practical problems (higher switching voltage and transient-induced latchup issue) limiting the use of SCR-based devices in on-chip ESD protection are reported Some modified device structures and trigger-assist circuit techniques to reduce the switching voltage of SCR-based devices are discussed The solutions to overcome latchup issue in the SCR-based devices are also discussed to safely apply the SCR-based devices for on-chip ESD protection in CMOS IC products

224 citations


Cites methods from "Latchup-free ESD protection design ..."

  • ...Moreover, some advanced trigger-assist circuit techniques had been also reported to enhance the turn-on speed of SCR device, such as the gate-coupled technique [21], the hot-carrier triggered technique [22], the GGNMOS-triggered technique [23], [24], the substrate-triggered technique [25], [26], double-triggered technique [27], native-NMOS-trigger technique [28], etc....

    [...]

  • ...stacked diode string [26], had been reported to have 7-kV HBM ESD level and free to latchup issue in a 0....

    [...]

  • ...Substrate-Triggered SCR (STSCR) [25], [26]...

    [...]

Journal ArticleDOI
Fei Ma1, Bin Zhang1, Yan Han1, Jianfeng Zheng1, Bo Song1, Shurong Dong1, Liang Hailian1 
TL;DR: In this article, a ring-resistance-triggered stacked SCR-laterally diffused MOS was verified in a 0.35 μm, 30-V/5-V bipolar CMOS DMOS process to solve the coupling of trigger voltage and holding voltage.
Abstract: A novel ring-resistance-triggered stacked SCR-laterally diffused MOSs has been successfully verified in a 0.35 μm, 30-V/5-V bipolar CMOS DMOS process to solve the coupling of trigger voltage and holding voltage in stacking structures. The holding voltage of the proposed structure can be modulated by varying stacking numbers, and a high holding voltage of 22 V has been achieved using six stacks. On the other side, the trigger voltage almost keeps constant at ~ 53 V and a high failure current of 3.5 A has been achieved.

49 citations


Cites background from "Latchup-free ESD protection design ..."

  • ...holding current of the proposed structure can be flexibly tuned to satisfy the latch-up immunity requirement [9]....

    [...]

Patent
21 Jul 2005
TL;DR: In this paper, a semiconductor device for electrostatic discharge (ESD) protection comprises a silicon controlled rectifier (SCR), a substrate, a gate, a first diffused region, and a second diffused regions separated apart from the first region.
Abstract: A semiconductor device for electrostatic discharge (ESD) protection comprises a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the first well to serve as an anode, and a first n-type region partially formed in the second well to serve as a cathode, a p-type metal-oxide-semiconductor (PMOS) transistor formed in the first well including a gate, a first diffused region and a second diffused region separated apart from the first diffused region, a second n-type region formed in the first well electrically connected to the first diffused region of the PMOS transistor, and a second p-type region formed in the substrate electrically connected to the second diffused region of the PMOS transistor.

45 citations

Journal ArticleDOI
TL;DR: In this paper, an ultra-low-leakage power-rail ESD clamp circuit, composed of the SCR device and new ESD detection circuit, was proposed with consideration of gate current to reduce the standby leakage current.
Abstract: An ultra-low-leakage power-rail ESD clamp circuit, composed of the SCR device and new ESD detection circuit, has been proposed with consideration of gate current to reduce the standby leakage current. By controlling the gate current of the devices in the ESD detection circuit under a specified bias condition, the whole power-rail ESD clamp circuit can achieve an ultra-low standby leakage current. The new proposed circuit has been fabricated in a 1 V 65 nm CMOS process for experimental verification. The new proposed power-rail ESD clamp circuit can achieve 7 kV HBM and 325 V MM ESD levels while consuming only a standby leakage current of 96 nA at 1 V bias in room temperature and occupying an active area of only 49 mum 21 mum.

41 citations

01 Jan 2009
TL;DR: An ultra-low-leakage power-rail ESD clamp circuit, composed of the SCR device and new ESD detection circuit, has been proposed with consideration of gate current to reduce the standby leakage current.
Abstract: An ultra-low-leakage power-rail ESD clamp circuit, composed of the SCR device and new ESD detection circuit, has been proposed with consideration of gate current to reduce the standby leakage current. By controlling the gate current of the de- vices in the ESD detection circuit under a specified bias condition, the whole power-rail ESD clamp circuit can achieve an ultra-low standby leakage current. The new proposed circuit has been fabri- cated in a 1 V 65 nm CMOS process for experimental verification. The new proposed power-rail ESD clamp circuit can achieve 7 kV HBM and 325 V MM ESD levels while consuming only a standby leakage current of 96 nA at 1 V bias in room temperature and oc- cupying an active area of only 49 m 21 m. Index Terms—Electrostatic discharge (ESD), gate leakage, power-rail ESD clamp circuit, silicon controlled rectifier (SCR).

36 citations


Cites methods from "Latchup-free ESD protection design ..."

  • ...The p-type substrate-triggered silicon-controlled rectifier (SCR) device is used as the main ESD clamping device [11]....

    [...]

References
More filters
Book
01 Jan 1995
TL;DR: ESD Phenomena and Test Methods The Physics of ESD Protection Circuit Elements Requirements and Synthesis of ESD Protection Circuits Design and Layout Requirements Analysis and Case Studies Modelling of ESC in Integrated Circuits Effects of Processing and Packaging.
Abstract: ESD Phenomena and Test Methods The Physics of ESD Protection Circuit Elements Requirements and Synthesis of ESD Protection Circuits Design and Layout Requirements Analysis and Case Studies Modelling of ESD in Integrated Circuits Effects of Processing and Packaging.

554 citations


"Latchup-free ESD protection design ..." refers background in this paper

  • ...I. INTRODUCTION ON-CHIP ESD protection circuits have to be added be-tween the input/output (I/O) pads and / to provide the desired electrostatic discharge (ESD) robustness in CMOS integrated circuits (ICs) [1]....

    [...]

Journal ArticleDOI
TL;DR: In this paper, a whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits is proposed to provide a real whole chip ESDprotection for submicron CMOS IC's without causing unexpected ESD damage in the internal circuits.
Abstract: A whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits is proposed to provide a real whole-chip ESD protection for submicron CMOS IC's without causing unexpected ESD damage in the internal circuits. The efficient VDD-to-VSS ESD clamp circuit has been designed to provide a low-impedance path between the VDD and VSS power lines of the IC during the ESD-stress condition, but this ESD clamp circuit is kept off when the IC is under its normal operating condition. Due to the parasitic resistance and capacitance along the VDD and VSS power lines, the ESD-protection efficiency is dependent on the pin location on a chip. Therefore, an experimental test chip has been designed and fabricated to build up a special ESD design rule for whole-chip ESD protection in a 0.8-/spl mu/m CMOS technology. This whole-chip ESD protection design has been practically used to rescue a 0.8-/spl mu/m CMOS IC product with a pin-to-pin HBM ESD level from the original level of 0.5 kV to become above 3 kV.

323 citations

Journal ArticleDOI
TL;DR: In this article, a novel silicon-controlled rectifier (SCR) structure for on-chip protection against electrostatic discharge (ESD) stress at output or input pads is presented, which switches to an ON state at a trigger voltage determined by the gate length of an incorporated nMOS-like structure.
Abstract: A novel silicon-controlled rectifier (SCR) structure for on-chip protection against electrostatic discharge (ESD) stress at output or input pads is presented. The SCR switches to an ON state at a trigger voltage determined by the gate length of an incorporated nMOS-like structure. Thus, the new SCR can be designed to consistently trigger at a voltage low enough to protect nMOS transistors from ESD. The capability of a protection circuit using the new SCR design is experimentally demonstrated. The tunability of the SCR trigger voltage with reference to the nMOS breakdown voltage is exploited to improve the human body model (HBM) ESD failure threshold of an output buffer from 1500 to 5000 V. >

281 citations

Proceedings Article
01 Sep 2001
TL;DR: A novel Grounded-Gate NMOS Triggered SCR device (GGSCR) is introduced and compared to the LVTSCR, demonstrating that GGSCRs can fulfill all ESD protection requirements for todays IC applications in different 0.25 um, 0.18 um and 0.13 um CMOS processes.
Abstract: In this paper, design aspects, operation, protection capability and applications of SCRs in deep sub-micron CMOS are addressed. A novel Grounded-Gate NMOS Triggered SCR device (GGSCR) is introduced and compared to the LVTSCR. Experimental verification, including endurance testing, demonstrates that GGSCRs can fulfill all ESD protection requirements for todays IC applications in different 0.25 um, 0.18 um and 0.13 um CMOS processes.

121 citations