LC-VCO Design Optimization Methodology Based on the $g_m/I_D$ Ratio for Nanometer CMOS Technologies
Summary (3 min read)
Introduction
- An LC-VCO design optimization methodology based on the gm/ID technique and on the exploration of all inversion regions of the MOS transistor is presented.
- Secondly, its value gives a direct indication of the inversion region and of the efficiency of the transistor in translating current consumption into transconductance.
- Several RF blocks designed in CMOS technologies and working in MI or WI have been reported in the last decade.
- This idea considers the conservative limit where the MOS transistor frequency is below the quasistatic-limit frequency of one tenth of fT [4], with fT the MOST transition frequency.
- In third place is the modeling of the LC-VCO, where the expressions of phase noise (L), output voltage Vout and VCO flicker corner frequency fc,1/f3 are reordered to make them function of gm/ID and i.
II. MOS TRANSISTOR ANALYSIS
- The first step of the methodology, in order to generate a database with its three most important characteristic data, is the correct modeling of the MOST in DC behaviour and in small signal, low frequency of operation.
- Firstly, the transconductance to current ratio gm/ID versus i is used to give an indication of the transistor operation region as well as for calculating MOST dimensions.
- Finally the noise constants have to be known.
- Because of the slight variation in the curves for such a large width range, the methodology presented here succeeds.
- To acquire the required characteristics curves for this semi-empirical model, a very simple scheme is utilized: transistor gate and drain nodes are connected to October 29, 2013 DRAFT 6 a DC voltage source, while source and bulk nodes are connected either to ground (nMOS transistor) or to the supply voltage (pMOS transistor).
III. ANALYSIS OF PASSIVE COMPONENTS
- The second step in the methodology is the characterization of passive components.
- Their characterization can be done either by semi-empirical models of library cells provided by the foundry or by electromagnetic solvers such as ASITIC [18] or ADSTMMomentum.
- Looking for biunivocal relationships between Lind and Rind, computational routines are implemented to find, for a particular inductance value, the nearest best inductor.
- The nMOS and pMOS sizing is done in order to match the pMOS and nMOS transconductances, gm,p and gm,n, i.e gm,n = gm,p = gm.
A. Phase noise model
- Phase noise L is a fundamental characteristic of a VCO that describes its spectral purity around its oscillation frequency f0 [20].
- Considering a frequency offset ∆f around f0, three asymptotic zones can be defined [21].
- Particularly, the flicker corner frequency fc,1/f3 is the VCO parameter that defines the lower limit of the 1/f2 zone.
- The equations formulated before, particularly (11) and (14), help us to quantitatively visualize the compromises between phase noise and current consumption.
- Considering a fixed gm, imposed by (9), when gm/ID rises, i.e when moving towards weak inversion, ID decreases in the same proportion.
V. PROPOSED DESIGN METHODOLOGY
- The methodology proposed hereafter intends to give a simple way to size the LC-VCO components and to visualize graphically the trade-offs inherent in the design.
- The flow diagram of the method is represented in Fig. 7, and it is organized in the following steps: Step 1: Start fixing a set of initial parameters and limits: minimum transistor channel length Lmin, safety margin factor kosc, maximum equivalent inductance Lind,max, minimum varactor capacitance Cvar,min and Cload.
- Pick a pair of values of inductor Lind and gm/ID ratio, from the technological database of inductors and transistors, which is assumed previously collected, also known as Step 2.
- Extract the transistors equivalent capacitance from C ′ nMOS vs. i and C ′ pMOS vs. i tables.
- Calculate the phase noise L1/f2 using (11) at the frequency offset ∆f .
A. Design maps
- The authors implemented the design flow in a set of computational routines to graphically study the behavior of the phase noise, the current consumption and the flicker corner frequency when gm/ID and Lind change.
- The relation between ID and gm/ID, for various inductor values, is plotted in Fig. 8 (left axis).
- This implies a reduction in gind, and thus in gm, due to (9).
- Phase noise increases when working in moderate and weak inversion because it is proportional to gm/ID as states (11).
- Because MOST corner frequency decreases when moving towards weak October 29, 2013 DRAFT 15 inversion, the flicker corner also decreases in weak inversion.
VI. APPLICATION EXAMPLES
- In this section four 2.4 GHz LC-VCOs designed in a 90 nm CMOS technology are presented.
- A drain current constraint of ID,max ≤ 400µA was set and it is shown in the shadowed area of the figure.
- Table I compares the VCO parameters obtained by the design flow formulas with the derived ones through SpectreRF analysis.
- Analyzing designs P3 and P4, the authors observe that the first one consumes 16% less and has a phase noise only 1dB higher than the second, but it is far below the quasistatic-limit frequency, therefore it is not recommendable to choose P3 when f0 = 2.4 GHz.
- Finally, design P4 is chosen to validate experimentally the methodology.
VII. EXPERIMENTAL RESULTS
- The characteristics of the VCO were measured on die using a microprobe station.
- Unfortunately, the buffer does not work properly and interferes with the VCO behaviour, so necessary the measurements were done with the output buffer switched off.
- Γav rises to approximately 0.4, and the computed fc,1/f3 is 257 kHz, very near the measured data.
- The current ID was also swept to 310 µA and a set of phase noise measurements at 400 kHz from the carrier were performed (forty measurements of L were taken for each current value), as depicted in Fig. 15, considering again a carrier frequency around 2.16 GHz.
- Table II compares the performance of the designed LC-VCO in moderate inversion with that of some prior works, where the well known figure-of-merit (FoM) of the VCO defined in [22] is used.
VIII. CONCLUSIONS
- An RF LC-VCO design methodology for nanometer technologies based on the gm/ID technique has been presented.
- The methodology proposed enables a considerable design time reduction October 29, 2013 DRAFT 17 as little re-design is needed.
- Plots of several variables involved in the VCO design were shown and compromises with the inversion region or the selection of the inductor were highlighted.
- For simplicity the authors will consider that no correlation exists between them.
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Citations
56 citations
Cites background or methods from "LC-VCO Design Optimization Methodol..."
...Various CMOS analog RF designs biased in MI and WI have been reported, as shown in [1]–[9], among others, where a considerable power reduction is achieved compared with biasing in strong inversion....
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...This way, it jointly considers second and higher order effects which appear in nanometer technologies, as discussed in [9]....
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...In this paper, the design method used follows the guidelines the authors enunciate in [9]; i....
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...In this sense, this paper follows the same approach of [9]–[18], where optimization techniques for RF circuits applied before electrical simulation are proven as a suitable design strategy....
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32 citations
29 citations
24 citations
22 citations
Cites methods from "LC-VCO Design Optimization Methodol..."
...Our analyses will allow for the first time to gain insight into the theoretical details of this technique and its effective application, in addition to the oscillator performance optimization with respect to transconductance-to-current ratio (gm/ID); for example, [22]....
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References
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Additional excerpts
...October 29, 2013 DRAFT 14...
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604 citations
"LC-VCO Design Optimization Methodol..." refers background or methods in this paper
...The MOST intrinsic gain Ai, defined as the gain of a common source transistor amplifier loaded by an ideal current source [2], is Ai = gm/gds = (gm/ID)/(gds/ID)....
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...This is achieved by using the ratio of transconductance to drain current gm/ID methodology presented in [2], [3] and taking advantage of operation in all the inversion regions (weak, moderate and strong) of the MOS transistor (MOST) [4]....
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358 citations
"LC-VCO Design Optimization Methodol..." refers background in this paper
...As these two characteristics are directly related, their trade-off has to be achieved optimizing the design of RF blocks....
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Frequently Asked Questions (19)
Q2. What is the expression of phase noise for an arbitrary oscillator?
The expression of phase noise for an arbitrary oscillator in the 1/f2 region of the phase noise spectrumexpressed by Hajimiri in [20] isL1/f2(∆f) = 10 log ( Γ2rms q2max i2n/∆f 2∆f2 ) (16)October 29, 2013 DRAFT18where Γrms is the rms value of the impulse sensitivity function ISF defined in [20], qmax is the maximum charge displacement across the capacitor in the output nodes, ∆f is the frequency offset respect to the oscillation frequency f0, and i2n/∆f is the power spectral density of the noise source considered at the output nodes.
Q3. Why is a semi-empirical MOS model used?
In this paper, a semi-empirical MOS model is utilized to describe the MOST because it considers the second and higher order effects of nanometer technologies, and it is easily obtained by extracting MOS characteristics via DC simulation.
Q4. What is the inductor in the work?
In this work, the best inductor is considered the one with the highest parallel resistance, since it will lead to the lowest required transconductance and hence consumption, as it will be shown in Section IV.
Q5. What is the simplest way to obtain the characteristics curves for the MOST?
To acquire the required characteristics curves for this semi-empirical model, a very simple scheme is utilized: transistor gate and drain nodes are connected toOctober 29, 2013 DRAFT6 a DC voltage source, while source and bulk nodes are connected either to ground (nMOS transistor) or to the supply voltage (pMOS transistor).
Q6. What is the maximum value of gvar over the varactor control voltage range?
For the accumulation nMOS varactors used in the design presented in Section VI, the maximum value of gvar over the varactor control voltage range is approximately 70 µS; so varactor conductance can be ignored compared to the conductances of the other VCO components.
Q7. What is the first step of the methodology?
The first step of the methodology, in order to generate a database with its three most important characteristic data, is the correct modeling of the MOST in DC behaviour and in small signal, low frequency of operation.
Q8. What is the phase noise expression for the 1/f2 region of the spectrum?
In the 1/f2 region of the spectrum (see Appendix A for derivation) the phase noise expression isL1/f2(∆f) = 10log ( kBT π264 1 Q2 gm ID 1 ID f20 ∆f2λ )(11)where λ = γαeq + 1 kosc , γ is the excess noise factor, kB is the Boltzmann constant, T is the absolute temperature, f0 is the oscillation frequency, ∆f is the frequency offset and αeq is defined asαeq = (gd0,n gm,n + gd0,p gm,p )−1 (12)with gd0,n and gd0,p the zero-bias (i.e VDS = 0) drain conductances gds, for nMOS and pMOS respectively.
Q9. How much is the minimum measured ID?
The minimum measured ID where the VCO works, for three samples’ average, is 62.5 µA; 13.5% higher than the expected value of 52 µA obtained from the design flow.
Q10. What is the value of the gain of a common source transistor amplifier loaded by an ideal current?
defined as the gain of a common source transistor amplifier loaded by an ideal current source [2], is Ai = gm/gds = (gm/ID)/(gds/ID).
Q11. How many widths should be used to get a complete dataset?
To get a very complete dataset the same simulation should be run for a set of widths (for example, the set chosen for Fig. 1), when a fixed transistor length value is used.
Q12. What is the sizing of the nMOS and pMOS transistors?
In this paper, the nMOS and pMOS sizing is done in order to match the pMOS and nMOS transconductances, gm,p and gm,n, i.e gm,n = gm,p = gm.
Q13. What is the noise constant in the MOST?
In this work the authors have considered these two constants: a) the excess noise factor λ of the white noise [5], and b) the flicker noise constant KF (or K ′ f , if it is divided by the MOS normalized oxide capacitance C ′ox).
Q14. How can the authors obtain the noise values from the MOST?
λ and KF values should be obtained from handling MOST noise data provided by the foundry or estimated from simulations or measurements [17].
Q15. what is the inverse of the gm/ID?
substituting (23) and (25) in (16), considering Γrms ≈ 0.5 due to the symmetry characteristicsof this VCO, and reordering the terms, the authors obtainL1/f2(∆f) = 10 log ( kBT π282 λ 1 Q2 gm ID 1 ID f20 ∆f2) (26)B. Expression of phase noise of a LC-VCO in the 1/f3 spectrum region.
Q16. What is the difference between the two designs?
Analyzing designs P3 and P4, the authors observe that the first one consumes 16% less and has a phase noise only 1dB higher than the second, but it is far below the quasistatic-limit frequency, therefore it is not recommendable to choose P3 when f0 = 2.4 GHz.
Q17. What are the drawbacks of electromagnetic solver?
Electromagnetic solver has major drawbacks: 1) the need to have the technological data provided by the foundry to obtain accurate descriptions, and 2) the high computational time spent to obtain the solutions.
Q18. How do you calculate the phase noise?
October 29, 2013 DRAFT14The authors implemented the design flow in a set of computational routines to graphically study the behavior of the phase noise, the current consumption and the flicker corner frequency when gm/ID and Lind change.
Q19. What is the equivalent capacitance of the MOS transistor?
Considering the five capacitance model of the MOS transistor, the equivalent cross-coupled transistorcapacitance CMOS , valid both for the nMOS and pMOS transistors, isCMOS = 4Cgd + (Cgs + Cgb + Cdb + Cds).