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Journal ArticleDOI

LC-VCO Design Optimization Methodology Based on the $g_m/I_D$ Ratio for Nanometer CMOS Technologies

29 Apr 2011-IEEE Transactions on Microwave Theory and Techniques (Institute of Electrical and Electronics Engineers)-Vol. 59, Iss: 7, pp 1822-1831
TL;DR: In this article, an LC voltage-controlled oscillator (LC VCO) design optimization methodology based on the gm/ID tech nique and on the exploration of all inversion regions of the MOS transistor (MOST) is presented.
Abstract: In this paper, an LC voltage-controlled oscillator (LC VCO) design optimization methodology based on the gm/ID tech nique and on the exploration of all inversion regions of the MOS transistor (MOST) is presented. An in-depth study of the com promises between phase noise and current consumption permits optimization of the design for given specifications. Semiempirical models of MOSTs and inductors, obtained by simulation, jointly with analytical phase noise models, allow to get a design space map where the design tradeoffs are easily identified. Four LC-VCO designs in different inversion regions in a 90-nm CMOS process are obtained with the proposed methodology and verified with electrical simulations. Finally, the implementation and measurements are presented for a 2.4-GHz VCO operating in moderate inversion. The designed VCO draws 440 μA from a 1.2-V power supply and presents a phase noise of -106.2 dBc/Hz at 400 kHz from the carrier.

Summary (3 min read)

Introduction

  • An LC-VCO design optimization methodology based on the gm/ID technique and on the exploration of all inversion regions of the MOS transistor is presented.
  • Secondly, its value gives a direct indication of the inversion region and of the efficiency of the transistor in translating current consumption into transconductance.
  • Several RF blocks designed in CMOS technologies and working in MI or WI have been reported in the last decade.
  • This idea considers the conservative limit where the MOS transistor frequency is below the quasistatic-limit frequency of one tenth of fT [4], with fT the MOST transition frequency.
  • In third place is the modeling of the LC-VCO, where the expressions of phase noise (L), output voltage Vout and VCO flicker corner frequency fc,1/f3 are reordered to make them function of gm/ID and i.

II. MOS TRANSISTOR ANALYSIS

  • The first step of the methodology, in order to generate a database with its three most important characteristic data, is the correct modeling of the MOST in DC behaviour and in small signal, low frequency of operation.
  • Firstly, the transconductance to current ratio gm/ID versus i is used to give an indication of the transistor operation region as well as for calculating MOST dimensions.
  • Finally the noise constants have to be known.
  • Because of the slight variation in the curves for such a large width range, the methodology presented here succeeds.
  • To acquire the required characteristics curves for this semi-empirical model, a very simple scheme is utilized: transistor gate and drain nodes are connected to October 29, 2013 DRAFT 6 a DC voltage source, while source and bulk nodes are connected either to ground (nMOS transistor) or to the supply voltage (pMOS transistor).

III. ANALYSIS OF PASSIVE COMPONENTS

  • The second step in the methodology is the characterization of passive components.
  • Their characterization can be done either by semi-empirical models of library cells provided by the foundry or by electromagnetic solvers such as ASITIC [18] or ADSTMMomentum.
  • Looking for biunivocal relationships between Lind and Rind, computational routines are implemented to find, for a particular inductance value, the nearest best inductor.
  • The nMOS and pMOS sizing is done in order to match the pMOS and nMOS transconductances, gm,p and gm,n, i.e gm,n = gm,p = gm.

A. Phase noise model

  • Phase noise L is a fundamental characteristic of a VCO that describes its spectral purity around its oscillation frequency f0 [20].
  • Considering a frequency offset ∆f around f0, three asymptotic zones can be defined [21].
  • Particularly, the flicker corner frequency fc,1/f3 is the VCO parameter that defines the lower limit of the 1/f2 zone.
  • The equations formulated before, particularly (11) and (14), help us to quantitatively visualize the compromises between phase noise and current consumption.
  • Considering a fixed gm, imposed by (9), when gm/ID rises, i.e when moving towards weak inversion, ID decreases in the same proportion.

V. PROPOSED DESIGN METHODOLOGY

  • The methodology proposed hereafter intends to give a simple way to size the LC-VCO components and to visualize graphically the trade-offs inherent in the design.
  • The flow diagram of the method is represented in Fig. 7, and it is organized in the following steps: Step 1: Start fixing a set of initial parameters and limits: minimum transistor channel length Lmin, safety margin factor kosc, maximum equivalent inductance Lind,max, minimum varactor capacitance Cvar,min and Cload.
  • Pick a pair of values of inductor Lind and gm/ID ratio, from the technological database of inductors and transistors, which is assumed previously collected, also known as Step 2.
  • Extract the transistors equivalent capacitance from C ′ nMOS vs. i and C ′ pMOS vs. i tables.
  • Calculate the phase noise L1/f2 using (11) at the frequency offset ∆f .

A. Design maps

  • The authors implemented the design flow in a set of computational routines to graphically study the behavior of the phase noise, the current consumption and the flicker corner frequency when gm/ID and Lind change.
  • The relation between ID and gm/ID, for various inductor values, is plotted in Fig. 8 (left axis).
  • This implies a reduction in gind, and thus in gm, due to (9).
  • Phase noise increases when working in moderate and weak inversion because it is proportional to gm/ID as states (11).
  • Because MOST corner frequency decreases when moving towards weak October 29, 2013 DRAFT 15 inversion, the flicker corner also decreases in weak inversion.

VI. APPLICATION EXAMPLES

  • In this section four 2.4 GHz LC-VCOs designed in a 90 nm CMOS technology are presented.
  • A drain current constraint of ID,max ≤ 400µA was set and it is shown in the shadowed area of the figure.
  • Table I compares the VCO parameters obtained by the design flow formulas with the derived ones through SpectreRF analysis.
  • Analyzing designs P3 and P4, the authors observe that the first one consumes 16% less and has a phase noise only 1dB higher than the second, but it is far below the quasistatic-limit frequency, therefore it is not recommendable to choose P3 when f0 = 2.4 GHz.
  • Finally, design P4 is chosen to validate experimentally the methodology.

VII. EXPERIMENTAL RESULTS

  • The characteristics of the VCO were measured on die using a microprobe station.
  • Unfortunately, the buffer does not work properly and interferes with the VCO behaviour, so necessary the measurements were done with the output buffer switched off.
  • Γav rises to approximately 0.4, and the computed fc,1/f3 is 257 kHz, very near the measured data.
  • The current ID was also swept to 310 µA and a set of phase noise measurements at 400 kHz from the carrier were performed (forty measurements of L were taken for each current value), as depicted in Fig. 15, considering again a carrier frequency around 2.16 GHz.
  • Table II compares the performance of the designed LC-VCO in moderate inversion with that of some prior works, where the well known figure-of-merit (FoM) of the VCO defined in [22] is used.

VIII. CONCLUSIONS

  • An RF LC-VCO design methodology for nanometer technologies based on the gm/ID technique has been presented.
  • The methodology proposed enables a considerable design time reduction October 29, 2013 DRAFT 17 as little re-design is needed.
  • Plots of several variables involved in the VCO design were shown and compromises with the inversion region or the selection of the inductor were highlighted.
  • For simplicity the authors will consider that no correlation exists between them.

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1
LC-VCO Design Optimization Methodology
Based on the g
m
/I
D
Ratio for Nanometer
CMOS Technologies
Rafaella Fiorelli, Eduardo Peral
´
ıas and Fernando Silveira,
Abstract
In this paper, an LC-VCO design optimization methodology based on the g
m
/I
D
technique and on
the exploration of all inversion regions of the MOS transistor is presented. An in-depth study of the
compromises between phase noise and current consumption permits optimization of the design for given
specifications. Semi-empirical models of MOS transistors and inductors, obtained by simulation, jointly
with analytical phase noise models, allow to get a design space map where the design trade-offs are
easily identified.
Four LC-VCO designs in different inversion regions in a 90 nm CMOS process are obtained with
the proposed methodology and verified with electrical simulations. Finally, the implementation and
measurements are presented for a 2.4 GHz VCO operating in moderate inversion. The designed VCO
draws 440 µA from a 1.2V power supply and presents a phase noise of 106.2 dBc/Hz at 400 kHz
from the carrier.
I. INTRODUCTION
The increasing demand of wireless applications with special emphasis on low power requirements
forces radio-frequency designers to work at the limits of the technology. To achieve these challeng-
ing specifications, best performance is mandatory in each block of the circuit, especially in terms of
power consumption, noise and linearity. In addition, since a few years ago, the extended use of CMOS
technologies enables RF designers to reduce costs as well as reaching good performance.
Rafaella Fiorelli and Eduardo Peral
´
ıas are with the Instituto de Microelectr
´
onica de Sevilla, CNM-CSIC, Seville, 41092, Spain
(e-mail:fiorelli@imse-cnm.csic.es, peralias@imse-cnm.csic.es).
Fernando Silveira is with the Instituto de Ingenier
´
ıa Elctrica, Universidad de la Rep
´
ublica, Montevideo, 11300, Uruguay
(e-mail:silveira@fing.edu.uy).
October 29, 2013 DRAFT

2
Fig. 1. (a) g
m
/I
D
and (b) g
ds
/I
D
vs. i = I
D
/(W/L) for four nMOS transistors and a V
DS
= 600 mV . Typical limits of
strong (SI), moderate (MI) and weak (WI) inversion regions are shown.
The requirements of an RF block, such as gain, noise or power consumption, strongly depend on the RF
application. For example, an application that is very demanding in terms of noise would need to accept
high power consumption, whereas a very low power design would cope with just enough non-very-low
noise values. As these two characteristics are directly related, their trade-off has to be achieved optimizing
the design of RF blocks. This work explores those compromises in order to optimize inductor-capacitor-
tank voltage controlled oscillators (LC-VCOs). This study is relevant as VCOs, due to their phase noise,
are responsible for most part of the error in the processed signal in an RF receiver [1], as well as for
a non-negligible percentage of the system current consumption. The mentioned optimization is done by
exploiting the consumption-spectral purity trade-off of the VCOs in order to use just the needed current
to fulfill the application requirements. This is achieved by using the ratio of transconductance to drain
current g
m
/I
D
methodology presented in [2], [3] and taking advantage of operation in all the inversion
regions (weak, moderate and strong) of the MOS transistor (MOST) [4].
The g
m
/I
D
ratio of a saturated MOST is directly related to its inversion level. The inversion level
is directly associated with the normalized current or current density, defined as i = I
D
/(W/L) and
dependent on the gate, source and drain voltages [5]–[7]. The relationship between g
m
/I
D
and i -and
hence I
D
for a certain MOST aspect ratio W/L- is biunivocal; a typical form of this curve can be
October 29, 2013 DRAFT

3
appreciated in Fig. 1(a). Several factors make the g
m
/I
D
ratio a very useful parameter for describing the
state of operation and performance of a MOST and exploring its design space. Firstly, the ease to write
circuit design expressions as a function of this parameter, since generally the transconductance or the
current are part of them. Secondly, its value gives a direct indication of the inversion region and of the
efficiency of the transistor in translating current consumption into transconductance. Finally, its variation
is constrained to a very small range, efficiently covered with a grid of some tens of values of g
m
/I
D
(e.g. from 3 V
1
to 28 V
1
for a nanometer bulk nMOS). Utilizing this variable on the expressions of
the VCO characteristics and sweeping g
m
/I
D
allows to obtain a set of design space maps of phase noise,
gain, power consumption, among others, as it will be shown in Section V. This graphical representation
helps the designer to study the evolution and trade-offs of some of these characteristics when working
in any of the three inversion regions.
The MOST channel length reduction, as it is shown below, permits the design of RF blocks in weak and
moderate inversion (WI/MI) with less power consumption than when they are biased in the traditional way,
in the strong inversion (SI) region. Several RF blocks designed in CMOS technologies and working in MI
or WI have been reported in the last decade. Porret et al. [8] and Melly et al. [9] present, respectively, the
design of a receiver and a transmitter working at 433 MHz in MI. Ramos et al. [10] showed a 950 MHz
LNA in MI-WI. The authors have presented an RF amplifier for 900 MHz [11] and a 2.4 GHz VCO [12]
both designed in MI regions. Lee and Mohammadi [13] presented a 2.4 GHz VCO design in WI whereas
Hsieh and Lu [14] designed a 5 GHz receiver front-end in MI and WI. Finally, Perumana et al. [15]
designed a subthreshold 2.4 GHz receiver. Although the mentioned works successfully take advantage of
working in these MOS regions of operation, they do not present a systematic methodology for choosing
the operating point. This issue is covered in this paper for LC-VCOs.
The effect of moving from SI through WI implies a considerable current reduction, but as a counterpart,
parasitic capacitances are higher as the transistor dimensions increase. That is why, with sub-micrometer
technologies, high frequency design in MI is limited to around one gigahertz [11]. Nowadays, the advent
of nanometer CMOS technologies prepared for radio-frequency designs enable to design in MI with
working frequencies of several gigahertz. This idea considers the conservative limit where the MOS
transistor frequency is below the quasistatic-limit frequency of one tenth of f
T
[4], with f
T
the MOST
transition frequency. To visualize these facts, f
T
and g
m
/I
D
versus I
D
are depicted in Fig. 2 for a pMOS
transistor in 90 nm technology. These results show that increasing I
D
(i.e. moving to SI) leads to a rise
in f
T
and a reduction in the g
m
/I
D
ratio. It is also appreciated in Fig. 3, where the relation between f
T
and g
m
/I
D
and the overdrive voltage V
OD
= V
GS
V
T
, a parameter classically utilized in RF designs
October 29, 2013 DRAFT

4
Fig. 2. g
m
/I
D
and f
T
versus I
D
of a pMOS transistor with an aspect ratio of 360 µm/100 nm.
Fig. 3. f
T
versus g
m
/I
D
and versus the overdrive voltage V
OD
for nMOS transistors.
to indicate the bias point, are depicted. These plots also show that, in spite of the considerable fall in f
T
when working in MI, the resulting value is enough to work in the RF range of some gigahertz.
The proposed optimization methodology follows four steps. First of all, the DC and low frequency,
small signal behaviour of the MOS transistor has to be reflected in suitable expressions or curves of
g
m
/I
D
, g
ds
/I
D
and intrinsic capacitances versus i, as it will be discussed in Section II. In second place
comes the extraction of the models for passive components, presented in Section III. In third place is the
modeling of the LC-VCO, where the expressions of phase noise (L), output voltage V
out
and VCO flicker
corner frequency f
c,1/f
3
are reordered to make them function of g
m
/I
D
and i. This step is presented
in Section IV. Finally, a design flow is provided; it organizes the necessary computations based on the
third step and the decisions constrained by the VCO specifications, while it uses the technological data
October 29, 2013 DRAFT

5
collected in the first two steps. This fourth phase is developed in Section V. Sections VI and VII validate
this design methodology, contrasting four VCO designs with their correspondent electrical simulations
as well as presents measurement results of a specific implementation. Section VIII summarizes the main
contributions of this work.
II. MOS TRANSISTOR ANALYSIS
The first step of the methodology, in order to generate a database with its three most important
characteristic data, is the correct modeling of the MOST in DC behaviour and in small signal, low
frequency of operation. Firstly, the transconductance to current ratio g
m
/I
D
versus i is used to give an
indication of the transistor operation region as well as for calculating MOST dimensions. Secondly, the
output conductance g
ds
is also considered because in nanometer technologies this value is considerably
increased, and especially for LC-VCOs it affects the final transconductance value. The ratio g
ds
/I
D
versus i is also applied here [3]. In third place, the MOST intrinsic capacitances are included because,
in RF, they substantially modify the circuit behaviour. Considering the quasistatic limit frequency, only
C
ij
, with ij={gs, gd, gb, bs, bd}, are included. In order to simplify the modeling, the capacitances are
considered to be proportional to the MOST gate area, W L. Hence, each normalized MOST capacitance
C
0
ij
= C
ij
/(W L) is considered equal for all transistors for a specific width range. Because C
0
ij
are also
dependent on the inversion zone, the curve C
0
ij
versus i is used. Finally the noise constants have to be
known. In this work we have considered these two constants: a) the excess noise factor λ of the white
noise [5], and b) the flicker noise constant K
F
(or K
0
f
, if it is divided by the MOS normalized oxide
capacitance C
0
ox
).
The g
m
/I
D
, g
ds
/I
D
and C
0
ij
versus i curves vary only slightly with MOST width and length [3]; this
change is only non-negligible in very narrow devices. Fig. 1(b) shows, for a 100 nm nMOS transistor,
and four widths W = {360 nm, 3.6 µm, 36 µm, 360 µm}, the simulated results of the curves of g
m
/I
D
and g
ds
/I
D
versus i. For this technology, the spread of the curves is almost imperceptible. Because of
the slight variation in the curves for such a large width range, the methodology presented here succeeds.
In this paper, a semi-empirical MOS model is utilized to describe the MOST because it considers the
second and higher order effects of nanometer technologies, and it is easily obtained by extracting MOS
characteristics via DC simulation. The use of analytical compact models, such as EKV [5], ACM [6]
or PSP [16], have been discarded because the fitting of parameters is very time consuming; however,
if properly set, these models can also be used. To acquire the required characteristics curves for this
semi-empirical model, a very simple scheme is utilized: transistor gate and drain nodes are connected to
October 29, 2013 DRAFT

Citations
More filters
Journal ArticleDOI
TL;DR: In this paper, the MOS transistor (MOST) moderate-inversion (MI)-weakinversion region is shown to be the optimum design zone for CMOS 2.4 GHz common-source low-noise amplifiers (CS-LNAs) focused on low power consumption applications.
Abstract: In this paper, the MOS transistor (MOST) moderate-inversion (MI)-weak-inversion (WI) region is shown to be the optimum design zone for CMOS 2.4-GHz common-source low-noise amplifiers (CS-LNAs) focused on low power consumption applications. This statement is supported by a systematic study where the MOST is analyzed in all-inversion regions using an exhaustive CS-LNA noise-figure (NF)-power-consumption optimization technique with power gain constraint. Effects of bias choke resistance and MOST capacitances are carefully included in the study to obtain more accurate results, especially for the MI-WI region. NF, power consumption, and gain versus the inversion region are described with design space maps, providing the designer with a deep insight of their tradeoffs. The Pareto-optimal design frontier obtained by calculation-showing the MI-WI region as the optimum design zone-is reverified by extensive electrical simulations of a high number of designs. Finally, one 90-nm 2.4-GHz CS-LNA Pareto optimal design is implemented. It achieves the best figure of merit considering under-milliwatt CS-LNAs published designs, consuming 684 μW, an NF of 4.36 dB, a power gain of 9.7 dB, and a third-order intermodulation intercept point of -4 dBm with load and source resistances of 50 Ω.

56 citations


Cites background or methods from "LC-VCO Design Optimization Methodol..."

  • ...Various CMOS analog RF designs biased in MI and WI have been reported, as shown in [1]–[9], among others, where a considerable power reduction is achieved compared with biasing in strong inversion....

    [...]

  • ...This way, it jointly considers second and higher order effects which appear in nanometer technologies, as discussed in [9]....

    [...]

  • ...In this paper, the design method used follows the guidelines the authors enunciate in [9]; i....

    [...]

  • ...In this sense, this paper follows the same approach of [9]–[18], where optimization techniques for RF circuits applied before electrical simulation are proven as a suitable design strategy....

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TL;DR: An automatic synthesis of three typical blocks of nowadays RF front-end receivers, a narrowband differential low-noise amplifier, a mixer and a local oscillator, is presented, proving the surplus value of using an automatic IC design tool in RF circuitry synthesis.

32 citations

Journal ArticleDOI
TL;DR: Inventions within an alternative framework that uses precomputed look-up tables (LUTs) to enable fast and accurate evaluation of circuit sizing scenarios without a simulator in the loop are described, enabling millions of queries within seconds on a standard computer.
Abstract: Design productivity remains an important aspect in the analog integrated circuit design industry, as growing competition and shorter design cycles pressure the traditional flow that involves time-consuming manual iterations in a circuit simulator. This paper describes innovations within an alternative framework that uses precomputed look-up tables (LUTs) to enable fast and accurate evaluation of circuit sizing scenarios without a simulator in the loop. It lets the designer explore and understand the design space boundaries in a systematic setting, thus supporting informed decision making and architectural innovation that is difficult to attain with fully automated, black-box sizing tools. Our discussion begins with an overview of the LUT-based design paradigm and its two primary variants: inverse design (finding design parameters that meet the specifications) and forward evaluation (sweeping design parameters to search the design space). In support of the latter, the core of our work focuses on improving the accuracy and speed of LUT access, enabling millions of queries within seconds on a standard computer. Large improvements over prior art are enabled using enhanced interpolation methods, which allow for a relatively large LUT grid spacing (hence small memory footprint) and yet accurate parameter lookup. We evaluate the efficacy of the proposed methods using two classical analog circuits, a bandgap reference and a folded cascode amplifier. In the bandgap example, we observe less than 1 ppm error between the LUT-predicted temperature coefficient and circuit simulation. In the folded-cascode example, one million design points are generated in only 4 seconds, providing the designer with useful maps that delineate the reachability of certain target specifications.

29 citations

Proceedings ArticleDOI
13 Oct 2011
TL;DR: A 2.4-GHz CMOS single ended-input differential-output front-end built with a common source low noise amplifier (CS-LNA) and a switched transconductor mixer (SW-MIX) is presented.
Abstract: A 2.4-GHz CMOS single ended-input differential-output front-end built with a common source low noise amplifier (CS-LNA) and a switched transconductor mixer (SW-MIX) is presented. The circuit is designed and optimized to work in a ZigBee receiver. Since this is a low power consumption standard, a single-ended LNA is preferred over a fully-differential topology because it leads to lower cost in area and power consumption. Also, moderate and weak inversions regions were selected for the operation of the principal transistors. The front-end prototype has been implemented in a 90 nm RF process and occupies a chip area of 0.74 mm2 including on-chip inductors. Very competitive results are observed: a maximum conversion gain (CG) of 30 dB, a DSB noise figure of 7.5 dB, a maximum IIP3 of −12.8 dBm and IIP2 of 14.4 dBm while it consumes 4.7 mW from a 1.2 V supply.

24 citations

Journal ArticleDOI
TL;DR: The analyses of three techniques for phase noise reduction in the complementary metal-oxide semiconductor (CMOS) Colpitts oscillator circuit topology show that the adoption of these techniques may lead to a potential phase noise Reduction up to 19 dB at a 1-MHz frequency offset for an oscillation frequency of 10 GHz.
Abstract: Summary This paper reports the analyses of three techniques for phase noise reduction in the complementary metal-oxide semiconductor (CMOS) Colpitts oscillator circuit topology. Namely, the three techniques are inductive degeneration, noise filter, and optimum current density. The design of the circuit topology is carried out in 28-nm bulk CMOS technology. The analytical expression of the oscillation frequency is derived and validated through circuit simulations. Moreover, the theoretical analyses of the three techniques are carried out and verified by means of circuit simulations within a commercial design environment. The results obtained for the inductive degeneration and noise filter show the existence of an optimum inductance for minimum phase noise. The results obtained for the optimum bias current density technique applied to a Colpitts oscillator circuit topology incorporating either inductive degeneration or noise filter show the existence of an optimum bias current density for minimum phase noise. Overall, the analyses show that the adoption of these techniques may lead to a potential phase noise reduction up to 19 dB at a 1-MHz frequency offset for an oscillation frequency of 10 GHz. © 2015 The Authors International Journal of Circuit Theory and Applications Published by John Wiley & Sons Ltd.

22 citations


Cites methods from "LC-VCO Design Optimization Methodol..."

  • ...Our analyses will allow for the first time to gain insight into the theoretical details of this technique and its effective application, in addition to the oscillator performance optimization with respect to transconductance-to-current ratio (gm/ID); for example, [22]....

    [...]

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Additional excerpts

  • ...October 29, 2013 DRAFT 14...

    [...]

Journal ArticleDOI
TL;DR: In this paper, a new design methodology based on a unified treatment of all the regions of operation of the MOS transistor is proposed for the design of CMOS analog circuits and especially suited for low power circuits where the moderate inversion region often is used.
Abstract: A new design methodology based on a unified treatment of all the regions of operation of the MOS transistor is proposed. It is intended for the design of CMOS analog circuits and especially suited for low power circuits where the moderate inversion region often is used because it provides a good compromise between speed and power consumption. The synthesis procedure is based on the relation between the ratio of the transconductance over DC drain current g/sub m//I/sub D/ and the normalized current I/sub D//(W/L). The g/sub m//I/sub D/ indeed is a universal characteristic of all the transistors belonging to a same process. It may be derived from experimental measurements and fitted with simple analytical models. The method was applied successfully to the design of a silicon-on-insulator (SOI) micropower operational transconductance amplifier (OTA).

604 citations


"LC-VCO Design Optimization Methodol..." refers background or methods in this paper

  • ...The MOST intrinsic gain Ai, defined as the gain of a common source transistor amplifier loaded by an ideal current source [2], is Ai = gm/gds = (gm/ID)/(gds/ID)....

    [...]

  • ...This is achieved by using the ratio of transconductance to drain current gm/ID methodology presented in [2], [3] and taking advantage of operation in all the inversion regions (weak, moderate and strong) of the MOS transistor (MOST) [4]....

    [...]

Journal ArticleDOI
TL;DR: In this paper, the authors describe the latest and most advanced surface potential-based model jointly developed by The Pennsylvania State University and Philips, which includes model structure, mobility and velocity saturation description, further development and verification of symmetric linearization method, recent advances in the computational techniques for the surface potential, modeling of gate tunneling current, inclusion of the retrograde impurity profile, and noise sources.
Abstract: This paper describes the latest and most advanced surface-potential-based model jointly developed by The Pennsylvania State University and Philips. Specific topics include model structure, mobility and velocity saturation description, further development and verification of symmetric linearization method, recent advances in the computational techniques for the surface potential, modeling of gate tunneling current, inclusion of the retrograde impurity profile, and noise sources. The emphasis of this paper is on incorporating the recent advances in MOS device physics and modeling within the compact modeling context

358 citations


"LC-VCO Design Optimization Methodol..." refers background in this paper

  • ...As these two characteristics are directly related, their trade-off has to be achieved optimizing the design of RF blocks....

    [...]

Frequently Asked Questions (19)
Q1. What have the authors contributed in "Lc-vco design optimization methodology based on the gm/id ratio for nanometer cmos technologies" ?

In this paper, an LC-VCO design optimization methodology based on the gm/ID technique and on the exploration of all inversion regions of the MOS transistor is presented. 

The expression of phase noise for an arbitrary oscillator in the 1/f2 region of the phase noise spectrumexpressed by Hajimiri in [20] isL1/f2(∆f) = 10 log ( Γ2rms q2max i2n/∆f 2∆f2 ) (16)October 29, 2013 DRAFT18where Γrms is the rms value of the impulse sensitivity function ISF defined in [20], qmax is the maximum charge displacement across the capacitor in the output nodes, ∆f is the frequency offset respect to the oscillation frequency f0, and i2n/∆f is the power spectral density of the noise source considered at the output nodes. 

In this paper, a semi-empirical MOS model is utilized to describe the MOST because it considers the second and higher order effects of nanometer technologies, and it is easily obtained by extracting MOS characteristics via DC simulation. 

In this work, the best inductor is considered the one with the highest parallel resistance, since it will lead to the lowest required transconductance and hence consumption, as it will be shown in Section IV. 

To acquire the required characteristics curves for this semi-empirical model, a very simple scheme is utilized: transistor gate and drain nodes are connected toOctober 29, 2013 DRAFT6 a DC voltage source, while source and bulk nodes are connected either to ground (nMOS transistor) or to the supply voltage (pMOS transistor). 

For the accumulation nMOS varactors used in the design presented in Section VI, the maximum value of gvar over the varactor control voltage range is approximately 70 µS; so varactor conductance can be ignored compared to the conductances of the other VCO components. 

The first step of the methodology, in order to generate a database with its three most important characteristic data, is the correct modeling of the MOST in DC behaviour and in small signal, low frequency of operation. 

In the 1/f2 region of the spectrum (see Appendix A for derivation) the phase noise expression isL1/f2(∆f) = 10log ( kBT π264 1 Q2 gm ID 1 ID f20 ∆f2λ )(11)where λ = γαeq + 1 kosc , γ is the excess noise factor, kB is the Boltzmann constant, T is the absolute temperature, f0 is the oscillation frequency, ∆f is the frequency offset and αeq is defined asαeq = (gd0,n gm,n + gd0,p gm,p )−1 (12)with gd0,n and gd0,p the zero-bias (i.e VDS = 0) drain conductances gds, for nMOS and pMOS respectively. 

The minimum measured ID where the VCO works, for three samples’ average, is 62.5 µA; 13.5% higher than the expected value of 52 µA obtained from the design flow. 

defined as the gain of a common source transistor amplifier loaded by an ideal current source [2], is Ai = gm/gds = (gm/ID)/(gds/ID). 

To get a very complete dataset the same simulation should be run for a set of widths (for example, the set chosen for Fig. 1), when a fixed transistor length value is used. 

In this paper, the nMOS and pMOS sizing is done in order to match the pMOS and nMOS transconductances, gm,p and gm,n, i.e gm,n = gm,p = gm. 

In this work the authors have considered these two constants: a) the excess noise factor λ of the white noise [5], and b) the flicker noise constant KF (or K ′ f , if it is divided by the MOS normalized oxide capacitance C ′ox). 

λ and KF values should be obtained from handling MOST noise data provided by the foundry or estimated from simulations or measurements [17]. 

substituting (23) and (25) in (16), considering Γrms ≈ 0.5 due to the symmetry characteristicsof this VCO, and reordering the terms, the authors obtainL1/f2(∆f) = 10 log ( kBT π282 λ 1 Q2 gm ID 1 ID f20 ∆f2) (26)B. Expression of phase noise of a LC-VCO in the 1/f3 spectrum region. 

Analyzing designs P3 and P4, the authors observe that the first one consumes 16% less and has a phase noise only 1dB higher than the second, but it is far below the quasistatic-limit frequency, therefore it is not recommendable to choose P3 when f0 = 2.4 GHz. 

Electromagnetic solver has major drawbacks: 1) the need to have the technological data provided by the foundry to obtain accurate descriptions, and 2) the high computational time spent to obtain the solutions. 

October 29, 2013 DRAFT14The authors implemented the design flow in a set of computational routines to graphically study the behavior of the phase noise, the current consumption and the flicker corner frequency when gm/ID and Lind change. 

Considering the five capacitance model of the MOS transistor, the equivalent cross-coupled transistorcapacitance CMOS , valid both for the nMOS and pMOS transistors, isCMOS = 4Cgd + (Cgs + Cgb + Cdb + Cds).