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LDO With Improved Common Gate Class-AB OTA Handles any Load Capacitors and Provides Fast Response to Load Transients

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TLDR
An LDO with fast response to load transients that can handle any practical capacitive loads that compares well against seven LDOs designed with common gate error amplifiers for similar levels of supply voltage, output voltage and current and against seven fast LDOs employing different error amplifier.
Abstract
This article proposes an LDO with fast response to load transients that can handle any practical capacitive loads. These features are mainly due to a novel frequency compensation circuit tailored for its error amplifier, which is based on an improved version of the popular common gate amplifier. A simple yet effective approach to the small-signal analysis of LDO with multiple feedback loops is employed to analyse intuitively the LDO and derive key design constraints. Simulation and measurement results performed on a test chip implemented in standard 130nm CMOS process validated the proposed LDO. It requires only $0.7\mu \text{A}$ quiescent current but exhibits an excellent response to load transients: when the load current jumps from 0A to 100mA in $1\mu \text{s}$ the output voltage presents an undershoot of 76mV and an overshoot of 198mV, without decoupling capacitors. It compares well against seven LDOs designed with common gate error amplifiers for similar levels of supply voltage, output voltage and current and against seven fast LDOs employing different error amplifiers. A figure-of-merit that considers the quiescent current, the maximum load current and capacitance, as well as the output voltage deviation, yielded a value for our LDO 39.8 times better than for the nearer competitor that employs common gate amplifier and 6 times better than the one employing a different error amplifier. When considering edge time and process scaling the performance of the proposed LDO is 4.8, respectively 4.5, times better than the second best in both comparisons.

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Journal ArticleDOI

A 340-nA-Quiescent 80-mA-Load 0.02-fs-FOM Active-Capacitor-Based Low-Dropout Regulator in Standard 0.18- μ m CMOS

TL;DR: In this paper, a low-dropout regulator (LDO) architecture based on an active capacitor is proposed to reduce both output variation and settling time under load step changes without using any passive capacitor.
Journal ArticleDOI

Fast LDO Handles a Wide Range of Load Currents and Load Capacitors, up to 100 mA and Over 1μF

TL;DR: In this article , a low dropout voltage regulator (LDO) was proposed, which exhibits both a fast response to load transients and the ability to handle practically any load capacitor.
Journal ArticleDOI

A Fast-Transient low-dropout regulator (LDO) With Super Class-AB OTA

TL;DR: In this article, a low power fast transient low-dropout regulator (LDO) employing a Super Class-AB operational transconductance amplifier (OTA) was proposed to achieve large charging/discharging current at the gate of power transistor, which not only shows excellent transient performance but also ensures enough line/load regulation.
Journal ArticleDOI

A fast-transient low-dropout regulator (LDO) with Super Class-AB OTA

TL;DR: In this paper , a low power fast transient low-dropout regulator (LDO) employing a Super Class-AB operational transconductance amplifier (OTA) was proposed to achieve large charging/discharging current at the gate of power transistor, which not only shows excellent transient performance but also ensures enough line/load regulation.
Journal ArticleDOI

Fast LDO Handles a Wide Range of Load Currents and Load Capacitors, up to 100 mA and Over 1μF

- 01 Jan 2022 - 
TL;DR: In this article , a low dropout voltage regulator (LDO) was proposed, which exhibits both a fast response to load transients and the ability to handle practically any load capacitor.
References
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Journal ArticleDOI

The Recycling Folded Cascode: A General Enhancement of the Folded Cascode Amplifier

TL;DR: A recycling amplifier architecture based on the folded cascode transconductance amplifier is described, which delivers an appreciably enhanced performance over that of the conventional folded by using previously idle devices in the signal path, which results in an enhanced transc conductance, gain, and slew rate.
Journal ArticleDOI

A 6- $\mu$ W Chip-Area-Efficient Output-Capacitorless LDO in 90-nm CMOS Technology

TL;DR: Experimental result verifies that the proposed LDO is stable for a capacitive load from 0 to 50 pF and with load capability of 100 mA and the gain-enhanced structure provides sufficient loop gain to improve line regulation and load regulation.
Journal ArticleDOI

A High Slew-Rate Push–Pull Output Amplifier for Low-Quiescent Current Low-Dropout Regulators With Transient-Response Improvement

TL;DR: A high slew-rate amplifier with push-pull output driving capability is proposed to enable an ultra-low quiescent current (Iq ~ 1muA) low-dropout (LDO) regulator with improved transient responses to improve stability of LDO regulators without using any on-chip and off-chip compensation capacitors.
Journal ArticleDOI

An Ultrafast Adaptively Biased Capacitorless LDO With Dynamic Charging Control

TL;DR: A common-gate error amplifier with high bandwidth and slew rate is proposed to reduce the output voltage spike and the response time of the LDO greatly and a faster and more accurate capacitorless LDO can be achieved.
Journal ArticleDOI

Simple technique using local CMFB to enhance slew rate and bandwidth of one-stage CMOS op-amps

TL;DR: In this paper, a simple modification to a one-stage op-amp for operation as a class AB amplifier leads to significant slew rate and bandwidth enhancement with essentially equal silicon area and static power dissipation requirements.
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