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Journal ArticleDOI

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

29 Apr 2003-Vol. 91, Iss: 2, pp 305-327
TL;DR: Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices and different circuit techniques to reduce the leakage power consumption are explored.
Abstract: High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.
Citations
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Journal ArticleDOI
14 Jun 2014
TL;DR: This paper exposes the vulnerability of commodity DRAM chips to disturbance errors, and shows that it is possible to corrupt data in nearby addresses by reading from the same address in DRAM by activating the same row inDRAM.
Abstract: Memory isolation is a key property of a reliable and secure computing system--an access to one memory address should not have unintended side effects on data stored in other addresses. However, as DRAM process technology scales down to smaller dimensions, it becomes more difficult to prevent DRAM cells from electrically interacting with each other. In this paper, we expose the vulnerability of commodity DRAM chips to disturbance errors. By reading from the same address in DRAM, we show that it is possible to corrupt data in nearby addresses. More specifically, activating the same row in DRAM corrupts data in nearby rows. We demonstrate this phenomenon on Intel and AMD systems using a malicious program that generates many DRAM accesses. We induce errors in most DRAM modules (110 out of 129) from three major DRAM manufacturers. From this we conclude that many deployed systems are likely to be at risk. We identify the root cause of disturbance errors as the repeated toggling of a DRAM row's wordline, which stresses inter-cell coupling effects that accelerate charge leakage from nearby rows. We provide an extensive characterization study of disturbance errors and their behavior using an FPGA-based testing platform. Among our key findings, we show that (i) it takes as few as 139K accesses to induce an error and (ii) up to one in every 1.7K cells is susceptible to errors. After examining various potential ways of addressing the problem, we propose a low-overhead solution to prevent the errors

999 citations


Cites background from "Leakage current mechanisms and leak..."

  • ..., subthreshold leakage [56] and gate-induced drain leakage [57]....

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Proceedings ArticleDOI
19 Jun 2010
TL;DR: An integrated power and performance prediction model for a GPU architecture to predict the optimal number of active processors for a given application and the outcome of IPP is used to control the number of running cores.
Abstract: GPU architectures are increasingly important in the multi-core era due to their high number of parallel processors. Performance optimization for multi-core processors has been a challenge for programmers. Furthermore, optimizing for power consumption is even more difficult. Unfortunately, as a result of the high number of processors, the power consumption of many-core processors such as GPUs has increased significantly. Hence, in this paper, we propose an integrated power and performance (IPP) prediction model for a GPU architecture to predict the optimal number of active processors for a given application. The basic intuition is that when an application reaches the peak memory bandwidth, using more cores does not result in performance improvement. We develop an empirical power model for the GPU. Unlike most previous models, which require measured execution times, hardware performance counters, or architectural simulations, IPP predicts execution times to calculate dynamic power events. We then use the outcome of IPP to control the number of running cores. We also model the increases in power consumption that resulted from the increases in temperature. With the predicted optimal number of active cores, we show that we can save up to 22.09%of runtime GPU energy consumption and on average 10.99% of that for the five memory bandwidth-limited benchmarks.

514 citations


Cites background from "Leakage current mechanisms and leak..."

  • ...Even though the evaluated GPU does not employ power gating, idle SMs do not consume as much power as active SMs do because of low-activity fa ctors [18] (i....

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Journal ArticleDOI
TL;DR: In this paper, a detailed theoretical model for the physics of strain effects in bulk semiconductors and surface Si, Ge, and III-V channel metal-oxide-semiconductor field effect transistors is presented.
Abstract: A detailed theoretical picture is given for the physics of strain effects in bulk semiconductors and surface Si, Ge, and III–V channel metal-oxide-semiconductor field-effect transistors. For the technologically important in-plane biaxial and longitudinal uniaxial stress, changes in energy band splitting and warping, effective mass, and scattering are investigated by symmetry, tight-binding, and k⋅p methods. The results show both types of stress split the Si conduction band while only longitudinal uniaxial stress along ⟨110⟩ splits the Ge conduction band. The longitudinal uniaxial stress warps the conduction band in all semiconductors. The physics of the strain altered valence bands for Si, Ge, and III–V semiconductors are shown to be similar although the strain enhancement of hole mobility is largest for longitudinal uniaxial compression in ⟨110⟩ channel devices and channel materials with substantial differences between heavy and light hole masses such as Ge and GaAs. Furthermore, for all these materials,...

467 citations

Journal ArticleDOI
TL;DR: This paper analyzes the read stability N-curve metrics and compares them with the commonly used static noise margin (SNM) metric defined by Seevinck, and demonstrates that the new metrics provide additional information in terms of current, which allows designing a more robust and stable cell.
Abstract: SRAM cell read stability and write-ability are major concerns in nanometer CMOS technologies, due to the progressive increase in intra-die variability and Vdd scaling. This paper analyzes the read stability N-curve metrics and compares them with the commonly used static noise margin (SNM) metric defined by Seevinck. Additionally, new write-ability metrics derived from the same N-curve are introduced and compared with the traditional write-trip point definition. Analytical models of all these metrics are developed. It is demonstrated that the new metrics provide additional information in terms of current, which allows designing a more robust and stable cell. By taking into account this current information, Vdd scaling is no longer a limiting factor for the read stability of the cell. Finally, these metrics are used to investigate the impact of the intra-die variability on the stability of the cell by using a statistically-aware circuit optimization approach and the results are compared with the worst-case or corner-based design

426 citations


Cites background from "Leakage current mechanisms and leak..."

  • ...The drain-induced-barrier lowering (DIBL) effect is included in all the operation regions of the transistor and represents the dependency of on [11]....

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  • ...Since has an exponential relation to the of the transistor [11], only this component is considered here....

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Proceedings ArticleDOI
07 Jun 2004
TL;DR: Results from the thermal model show that a temperature-aware design approach can provide more accurate estimations, and therefore better decisions and faster design convergence.
Abstract: Thermal design in sub-100nm technologies is one of the major challenges to the CAD community. In this paper, we first introduce the idea of temperature-aware design. We then propose a compact thermal model which can be integrated with modern CAD tools to achieve a temperature-aware design methodology. Finally, we use the compact thermal model in a case study of microprocessor design to show the importance of using temperature as a guideline for the design. Results from our thermal model show that a temperature-aware design approach can provide more accurate estimations, and therefore better decisions and faster design convergence.

346 citations


Additional excerpts

  • ...Keywords: temperature-aware design, temperature-aware computing, thermal model, power-aware design, leakage, reliability....

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References
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Book
01 Jan 1986

6,064 citations


"Leakage current mechanisms and leak..." refers background in this paper

  • ...Due to SCE in deep-submicrometer devices, subthreshold leakage current reduces significantly with voltage scaling [80]....

    [...]

Journal ArticleDOI
TL;DR: This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/.
Abstract: This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/. Scaling relationships are presented which show how a conventional MOSFET can be reduced in size. An improved small device structure is presented that uses ion implantation, to provide shallow source and drain regions and a nonuniform substrate doping profile. One-dimensional models are used to predict the substrate doping profile and the corresponding threshold voltage versus source voltage characteristic. A two-dimensional current transport model is used to predict the relative degree of short-channel effects for different device parameter combinations. Polysilicon-gate MOSFET's with channel lengths as short as 0.5 /spl mu/ were fabricated, and the device characteristics measured and compared with predicted values. The performance improvement expected from using these very small devices in highly miniaturized integrated circuits is projected.

3,008 citations


"Leakage current mechanisms and leak..." refers background in this paper

  • ...Based on constant field scaling [4], the SCE can be kept under control by scaling down the vertical dimensions, for example, gate insulator thickness, junction depth, along with the horizontal dimensions, while also proportionally decreasing the applied voltages....

    [...]

Book
Yuan Taur1, Tak H. Ning1
01 Jan 2016
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
Abstract: Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

2,680 citations


"Leakage current mechanisms and leak..." refers background in this paper

  • ...of source and drain regions [28]....

    [...]

  • ...The bulk charge that needs to be inverted is proportional to the area under the trapezoidal region given by Q / W (L+ L )=2, which is less than the total depletion charge in the long-channel case, which is Q / W (L) [28]....

    [...]

Book
01 Jan 1967
TL;DR: The Planar Technology of Semiconductor Surfaces is described in this article, where it is shown that the planar planar technology can be used to model the surface effects on p-n junction transistors.
Abstract: The Planar Technology. Solid-State Technology. Vapor-Phase Growth. Thermal Oxidation. Solid-State Diffusion. Semiconductors and Semiconductor Devices. Elements of Semiconductor Physics. Semiconductors under Non-Equilibrium Conditions. p-n Junction. Junction Transistor. Junction Field-Effect Transistors. Surface Effects and Surface-Controlled Devices. Theory of Semiconductor Surfaces. Surface Effects on p-n Junctions. Surface Field-Effect Transistors. Properties of the Silicon-Silicon Dioxide System.

2,394 citations

Book
29 Dec 1995
TL;DR: Digital Integrated Circuits as discussed by the authors is a practical book that bridges the gap between the circuit perspective and system perspective of digital integrated circuit design, including the impact of interconnect, design for low power, issues in timing and clocking, design methodologies and the tremendous effect of design automation on the digital design perspective.
Abstract: Progressive in content and form, this practical book successfully bridges the gap between the circuit perspective and system perspective of digital integrated circuit design. Digital Integrated Circuits maintains a consistent, logical flow of subject matter throughout. Addresses today's most significant and compelling industry topics, including: the impact of interconnect, design for low power, issues in timing and clocking, design methodologies, and the tremendous effect of design automation on the digital design perspective. For readers interested in digital circuit design.

1,348 citations