Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
Citations
999 citations
Cites background from "Leakage current mechanisms and leak..."
..., subthreshold leakage [56] and gate-induced drain leakage [57]....
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514 citations
Cites background from "Leakage current mechanisms and leak..."
...Even though the evaluated GPU does not employ power gating, idle SMs do not consume as much power as active SMs do because of low-activity fa ctors [18] (i....
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467 citations
426 citations
Cites background from "Leakage current mechanisms and leak..."
...The drain-induced-barrier lowering (DIBL) effect is included in all the operation regions of the transistor and represents the dependency of on [11]....
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...Since has an exponential relation to the of the transistor [11], only this component is considered here....
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346 citations
Additional excerpts
...Keywords: temperature-aware design, temperature-aware computing, thermal model, power-aware design, leakage, reliability....
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References
6,064 citations
"Leakage current mechanisms and leak..." refers background in this paper
...Due to SCE in deep-submicrometer devices, subthreshold leakage current reduces significantly with voltage scaling [80]....
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3,008 citations
"Leakage current mechanisms and leak..." refers background in this paper
...Based on constant field scaling [4], the SCE can be kept under control by scaling down the vertical dimensions, for example, gate insulator thickness, junction depth, along with the horizontal dimensions, while also proportionally decreasing the applied voltages....
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2,680 citations
"Leakage current mechanisms and leak..." refers background in this paper
...of source and drain regions [28]....
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...The bulk charge that needs to be inverted is proportional to the area under the trapezoidal region given by Q / W (L+ L )=2, which is less than the total depletion charge in the long-channel case, which is Q / W (L) [28]....
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2,394 citations
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