Leakage current reduction in CMOS VLSI circuits by input vector control
01 Feb 2004-IEEE Transactions on Very Large Scale Integration Systems (IEEE)-Vol. 12, Iss: 2, pp 140-154
TL;DR: Two runtime mechanisms for reducing the leakage current of a CMOS circuit are described and a design technique for applying the minimum leakage input to a sequential circuit is presented, which shows that it is possible to reduce the leakage by an average of 25% with practically no delay penalty.
Abstract: The first part of this paper describes two runtime mechanisms for reducing the leakage current of a CMOS circuit. In both cases, it is assumed that the system or environment produces a "sleep" signal that can be used to indicate that the circuit is in a standby mode. In the first method, the "sleep" signal is used to shift in a new set of external inputs and pre-selected internal signals into the circuit with the goal of setting the logic values of all of the internal signals so as to minimize the total leakage current in the circuit. This minimization is possible because the leakage current of a CMOS gate is strongly dependent on the input combination applied to its inputs. In the second method, nMOS and pMOS transistors are added to some of the gates in the circuit to increase the controllability of the internal signals of the circuit and decrease the leakage current of the gates using the "stack effect". This is, however, done carefully so that the minimum leakage is achieved subject to a delay constraint for all input-output paths in the circuit. In both cases, Boolean satisfiability is used to formulate the problems, which are subsequently solved by employing a highly efficient SAT solver. Experimental results on the combinational circuits in the MCNC91 benchmark suite demonstrate that it is possible to reduce the leakage current in combinational circuits by an average of 25% with only a 5% delay penalty. The second part of this paper presents a design technique for applying the minimum leakage input to a sequential circuit. The proposed method uses the built-in scan-chains in a VLSI circuit to drive it with the minimum leakage vector when it enters the sleep mode. The use of these scan registers eliminates the area and delay overhead of the additional circuitry that would otherwise be needed to apply the minimum leakage vector to the circuit. Experimental results on the sequential circuits in the MCNC91 benchmark suit show that, by using the proposed method, it is possible to reduce the leakage by an average of 25% with practically no delay penalty.
Citations
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16 Apr 2007
TL;DR: In this article, the authors show that for typical IC packages and cooling structures, a given amount of heat introduced at any position in the active layer will have similar impact on the average temperature of the layer.
Abstract: It has been the conventional assumption that, due to the superlinear dependence of leakage power consumption on temperature, and widely varying on-chip temperature profiles, accurate leakage estimation requires detailed knowledge of thermal profile. Leakage power depends on integrated circuit (IC) thermal profile and circuit design style. The authors show that linear models can be used to permit highly-accurate leakage estimation over the operating temperature ranges in real ICs. The authors then show that for typical IC packages and cooling structures, a given amount of heat introduced at any position in the active layer will have similar impact on the average temperature of the layer. These two observations allow us to prove that, for wide ranges of design styles and operating temperatures, extremely fast, coarse-grained thermal models, combined with linear leakage power consumption models, permit highly-accurate system-wide leakage power consumption estimation. The results of our proofs are further confirmed via comparisons with leakage estimation based on detailed, time-consuming thermal analysis techniques. Experimental results indicate that the proposed technique yields a 59,259times-1,790,000times speedup in leakage power estimation while maintaining accuracy
236 citations
TL;DR: A comprehensive assessment of state-of-the-art of dynamic power management (DPM) in wireless sensor networks is provided and aspects of power dissipation in a node are investigated and the strength and limitations of selective switching, dynamic frequency, and voltage scaling are analyzed.
Abstract: In the last few years, interest in wireless sensor networks has increased considerably. These networks can be useful for a large number of applications, including habitat monitoring, structural health monitoring, pipeline monitoring, transportation, precision agriculture, supply chain management, and many more. Typically, a wireless sensor network consists of a large number of simple nodes which operate with exhaustible batteries, unattended. Manual replacement or recharging the batteries is not an easy or desirable task. Hence, how energy is utilized by the various hardware subsystems of individual nodes directly affects the scope and usefulness of the entire network. This paper provides a comprehensive assessment of state-of-the-art of dynamic power management (DPM) in wireless sensor networks. It investigates aspects of power dissipation in a node and analyses the strength and limitations of selective switching, dynamic frequency, and voltage scaling.
128 citations
01 Jan 2006
TL;DR: An overview of the main sources of variability is presented and variation-tolerant circuit and microarchitectural approaches are surveyed.
127 citations
TL;DR: Since the leakage power increases much faster than the dynamic power at each new technology generation, LPA attacks are a serious threat to the information security of cryptographic circuits in sub-100-nm technologies.
Abstract: In this paper, a novel class of power analysis attacks to cryptographic circuits is presented. These attacks aim at recovering the secret key of a cryptographic core from measurements of its static (leakage) power. These attacks exploit the dependence of the leakage current of CMOS integrated circuits on their inputs (including the secret key of the cryptographic algorithm that they implement), as opposite to traditional power analysis attacks that are focused on the dynamic power. For this reason, this novel class of attacks is named ?leakage power analysis? (LPA). Since the leakage power increases much faster than the dynamic power at each new technology generation, LPA attacks are a serious threat to the information security of cryptographic circuits in sub-100-nm technologies. For the first time in the literature, a well-defined procedure to perform LPA attacks that is based on a solid theoretical background is presented. Advantages and measurement issues are also analyzed in comparison with traditional power analysis attacks based on dynamic power measurements. Examples are provided for various circuits, and an experimental attack to a register is performed for the first time. An analytical model of the LPA attack result is also provided to better understand the effectiveness of this technique. The impact of technology scaling is explicitly addressed by means of a simple analytical model and Monte Carlo simulations. Simulations on a 65- and 90-nm technology and experimental results are presented to justify the assumptions and validate the leakage power models that are adopted.
125 citations
Cites background from "Leakage current reduction in CMOS V..."
...Due to the strong leakage dependence on the input of digital circuits [8], leakage can also provide a significant amount of information on the secret key; hence, power analysis attacks based on leakage can be devised....
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...The leakage current of static CMOS logic gates strongly depends on their input [8]....
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TL;DR: Variability must be considered at both the circuit and micro-architectural design levels to keep pace with performance scaling and to keep power consumption within reasonable limits as mentioned in this paper, and an overview of the main sources of variability can be found in this paper.
Abstract: Parameter variations, which are increasing along with advances in process technologies, affect both timing and power. Variability must be considered at both the circuit and microarchitectural design levels to keep pace with performance scaling and to keep power consumption within reasonable limits. This article presents an overview of the main sources of variability and surveys variation-tolerant circuit and microarchitectural approaches
124 citations
References
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Book•
01 Jan 1990
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
2,758 citations
"Leakage current reduction in CMOS V..." refers methods in this paper
...In this section we introduce two methods to add control points to a circuit to decrease its leakage....
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TL;DR: In this article, a multithreshold-voltage CMOS (MTCMOS) based low-power digital circuit with 0.1-V power supply high-speed low power digital circuit technology was proposed, which has brought about logic gate characteristics of a 1.7ns propagation delay time and 0.3/spl mu/W/MHz/gate power dissipation with a standard load.
Abstract: 1-V power supply high-speed low-power digital circuit technology with 0.5-/spl mu/m multithreshold-voltage CMOS (MTCMOS) is proposed. This technology features both low-threshold voltage and high-threshold voltage MOSFET's in a single LSI. The low-threshold voltage MOSFET's enhance speed performance at a low supply voltage of 1 V or less, while the high-threshold voltage MOSFET's suppress the stand-by leakage current during the sleep period. This technology has brought about logic gate characteristics of a 1.7-ns propagation delay time and 0.3-/spl mu/W/MHz/gate power dissipation with a standard load. In addition, an MTCMOS standard cell library has been developed so that conventional CAD tools can be used to lay out low-voltage LSI's. To demonstrate MTCMOS's effectiveness, a PLL LSI based on standard cells was designed as a carrying vehicle. 18-MHz operation at 1 V was achieved using a 0.5-/spl mu/m CMOS process. >
1,338 citations
"Leakage current reduction in CMOS V..." refers methods in this paper
...In MTCMOS, a high threshold device is inserted in the series with low threshold transistors creating a sleep transistor....
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...Another possibility is to use multiple-threshold voltage CMOS (MTCMOS) [18]....
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TL;DR: In this article, the authors look closely at past trends in technology scaling and how well microprocessor technology and products have met these goals and project the challenges that lie ahead if these trends continue.
Abstract: Scaling advanced CMOS technology to the next generation improves performance, increases transistor density, and reduces power consumption. Technology scaling typically has three main goals: 1) reduce gate delay by 30%, resulting in an increase in operating frequency of about 43%; 2) double transistor density; and 3) reduce energy per transition by about 65%, saving 50% of power (at a 43% increase in frequency). These are not ad hoc goals; rather, they follow scaling theory. This article looks closely at past trends in technology scaling and how well microprocessor technology and products have met these goals. It also projects the challenges that lie ahead if these trends continue. This analysis uses data from various Intel microprocessors; however, this study is equally applicable to other types of logic designs. Is process technology meeting the goals predicted by scaling theory? An analysis of microprocessor performance, transistor density, and power trends through successive technology generations helps identify potential limiters of scaling, performance, and integration.
1,110 citations
04 Nov 2001
TL;DR: This paper generalizes various conflict driven learning strategies in terms of different partitioning schemes of the implication graph to re-examine the learning techniques used in various SAT solvers and propose an array of new learning schemes.
Abstract: One of the most important features of current state-of-the-art SAT solvers is the use of conflict based backtracking and learning techniques. In this paper, we generalize various conflict driven learning strategies in terms of different partitioning schemes of the implication graph. We re-examine the learning techniques used in various SAT solvers and propose an array of new learning schemes. Extensive experiments with real world examples show that the best performing new learning scheme has at least a 2/spl times/ speedup compared with learning schemes employed in state-of-the-art SAT solvers.
848 citations
"Leakage current reduction in CMOS V..." refers background in this paper
...SPICE simulator reports a leakage current value that includes both the subthreshold leakage and the gate leakage currents....
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Book•
01 Jan 2001
TL;DR: The design of next generation microprocessors in deep submicron CMOS technologies is covered, and a broad range of circuit styles and VLSI design techniques are covered, an indispensable reference for practicing circuit designers, architects, system designers, CAD tool developers, process technologists, and researchers.
Abstract: From the Publisher:
This book covers the design of next generation microprocessors in deep submicron CMOS technologies. The chapters in Design of High Performance Microprocessor Circuits were written by some of the worlds leading technologists, designers, and researchers. All levels of system abstraction are covered, but the emphasis rests squarely on circuit design. Examples are drawn from processors designed at AMD, Digital/Compaq, IBM, Intel, MIPS, Mitsubishi, and Motorola.
Each topic of this invaluable reference stands alone so the chapters can be read in any order. The following topics are covered in depth:
Architectural constraints of CMOS VLSI design Technology scaling, low-power devices, SOI, and process variations Contemporary design styles including a survey of logic families, robust dynamic circuits, asynchronous logic, self-timed pipelines, and fast arithmetic units Latches, clocks and clock distribution, phase-locked and delay-locked loops Register file, cache memory, and embedded DRAM design High-speed signaling techniques and I/O design ESD, electromigration, and hot-carrier reliability CAD tools, including timing verification and the analysis of power distribution schemes Test and testability
Design of High-Performance Microprocessor Circuits assumes a basic knowledge of digital circuit design and device operation, and covers a broad range of circuit styles and VLSI design techniques. Packed with practical know-how, it is an indispensable reference for practicing circuit designers, architects, system designers, CAD tool developers, process technologists, and researchers. It is also an essential text for VLSI design courses.
751 citations
"Leakage current reduction in CMOS V..." refers background in this paper
...This can be done using some high threshold transistors called sleep transistors [17]....
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