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Proceedings Article•DOI•

Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology

Chang-Tzu Wang1, Ming-Dou Ker1, Tien-Hao Tang2, Kuan-Cheng Su2•
National Chiao Tung University1, United Microelectronics Corporation2
18 May 2009-pp 21-24
TL;DR: In this paper, a low-leakage power-rail ESD clamp circuit was designed with consideration of gate current to reduce the total standby leakage current under normal circuit operating conditions.
Abstract: A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit, composed of the SCR device and new ESD detection circuit, has been designed with consideration of gate current to reduce the total standby leakage current under normal circuit operating conditions. After fabrication in a 1-V 65-nm fully-silicided CMOS process, the proposed power-rail ESD clamp circuit can sustain 7kV human-body-model (HBM) and 325V machine model (MM) ESD tests which occupying an silicon area of only 49µm×21µm and consuming a very low standby leakage current of 96nA at room temperature.

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References
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Journal Article•DOI•
Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI

[...]

Ming-Dou Ker
01 Jan 1999-IEEE Transactions on Electron Devices
TL;DR: In this paper, a whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits is proposed to provide a real whole chip ESDprotection for submicron CMOS IC's without causing unexpected ESD damage in the internal circuits.
Abstract: A whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits is proposed to provide a real whole-chip ESD protection for submicron CMOS IC's without causing unexpected ESD damage in the internal circuits. The efficient VDD-to-VSS ESD clamp circuit has been designed to provide a low-impedance path between the VDD and VSS power lines of the IC during the ESD-stress condition, but this ESD clamp circuit is kept off when the IC is under its normal operating condition. Due to the parasitic resistance and capacitance along the VDD and VSS power lines, the ESD-protection efficiency is dependent on the pin location on a chip. Therefore, an experimental test chip has been designed and fabricated to build up a special ESD design rule for whole-chip ESD protection in a 0.8-/spl mu/m CMOS technology. This whole-chip ESD protection design has been practically used to rescue a 0.8-/spl mu/m CMOS IC product with a pin-to-pin HBM ESD level from the original level of 0.5 kV to become above 3 kV.

323 citations

"Low-leakage electrostatic discharge..." refers methods in this paper

  • ...From the perspective on electrostatic discharge (ESD) protection, the power-rail ESD clamp circuit to effectively protect the core circuits is traditionally implemented by RCbased ESD protection structure with a large-sized ESD clamping MOSFET [4]....

    [...]

  • ...Table II shows the performance comparison among the traditional RC-based power-rail ESD clamp circuit [4], the modified ESD clamp circuit with timer level restorer [5], and the new proposed design of this work....

    [...]

  • ...Even if the leaky ESD clamping MOSFET is excluded, the standby leakage current of the stand-alone ESD detection circuit is still as large as 26.9µA at 125°C....

    [...]

  • ...V bias of the traditional RC-based ESD clamp circuit with the ESD clamping MOSFET (MESD) of W/L = 400µm/ 0.12µm at 25°C and 125°C are as large as 3.74µA and 44.8µA, respectively....

    [...]

  • ...The ESD clamping MOSFET cannot be completely turned off under the power-on condition due to the malfunction of the ESD detection circuit caused from the leakage current in the MOS capacitor, and in turn to induce extra large leakage current through ESD clamping MOSFET....

    [...]

Proceedings Article•
New considerations for MOSFET power clamps

[...]

Steven S. Poon1, Timothy J. Maloney1•
Intel1
01 Oct 2002
TL;DR: Two ESD clamp circuit design techniques have been developed to reduce cell size and to combat the effects of gate leakage that have become significant in recent generations of digital CMOS process technology.
Abstract: Two ESD clamp circuit design techniques have been developed to reduce cell size and to combat the effects of gate leakage that have become significant in recent generations of digital CMOS process technology. Such clamps have proven to be able to withstand HBM stresses of 6kV and CDM pulses of 1.2kV.

67 citations

"Low-leakage electrostatic discharge..." refers methods in this paper

  • ...Table II shows the performance comparison among the traditional RC-based power-rail ESD clamp circuit [4], the modified ESD clamp circuit with timer level restorer [5], and the new proposed design of this work....

    [...]

  • ...To solve the problem of malfunction in the traditional RCbased ESD detection circuit, the timer level restorer was ever reported [5]....

    [...]

Proceedings Article•DOI•
Nickel silicide metal gate FDSOI devices with improved gate oxide leakage

[...]

Zoran Krivokapic1, Witek Maszara1, K. Achutan1, P. King1, J. Gray1, M. Sidorow1, E. Zhao1, J. Zhang1, J. Chan1, A. Marathe1, Ming-Ren Lin1 •
Advanced Micro Devices1
08 Dec 2002
TL;DR: In this article, the authors demonstrate metal gate FDSOI devices using NiSi gates with symmetric V/sub t/ for both NMOS and PMOS devices and show capacitance equivalent gate oxide thickness (CET) 06 nm thinner than poly gates.
Abstract: Fully depleted SOI (FDSOI) devices with undoped channel require metal gates to achieve correct threshold voltages We demonstrate metal gate FDSOI devices using NiSi gates with symmetric V/sub t/ for both NMOS and PMOS devices Metal gates are stable on 2 nm gate oxide and show capacitance equivalent gate oxide thickness (CET) 06 nm thinner than poly gates The gate leakage current is up to two orders of magnitude lower and high mobility is achieved (peak electron mobility 670 cm/sup 2//Vs and 170 cm/sup 2//Vs for holes)

53 citations

"Low-leakage electrostatic discharge..." refers background in this paper

  • ...In 45-nm generation and beyond, the metal gate cooperated with high-k gate oxide is therefore applied to reduce the gate leakage current [2]....

    [...]

Journal Article•DOI•
Latchup-free ESD protection design with complementary substrate-triggered SCR devices

[...]

Ming-Dou Ker1, Kuo-Chun Hsu1•
National Chiao Tung University1
28 Jul 2003-IEEE Journal of Solid-state Circuits
TL;DR: In this article, latchup-free electrostatic discharge (ESD) protection circuits, which are combined with the substrate-triggered technique and an SCR device, are proposed.
Abstract: The turn-on mechanism of silicon-controlled rectifier (SCR) devices is essentially a current triggering event. While a current is applied to the base or substrate of an SCR device, it can be quickly triggered on into its latching state. In this paper, latchup-free electrostatic discharge (ESD) protection circuits, which are combined with the substrate-triggered technique and an SCR device, are proposed. A complementary circuit style with the substrate-triggered SCR device is designed to discharge both the pad-to-V/sub SS/ and pad-to-V/sub DD/ ESD stresses. The novel complementary substrate-triggered SCR devices have the advantages of controllable switching voltage, adjustable holding voltage, faster turn-on speed, and compatible to general CMOS process without extra process modification such as the silicide-blocking mask and ESD implantation. The total holding voltage of the substrate-triggered SCR device can be linearly increased by adding the stacked diode string to avoid the transient-induced latchup issue in the ESD protection circuits. The on-chip ESD protection circuits designed with the proposed complementary substrate-triggered SCR devices and stacked diode string for the input/output pad and power pad have been successfully verified in a 0.25-/spl mu/m salicided CMOS process with the human body model (machine model) ESD level of /spl sim/7.25 kV (500 V) in a small layout area.

50 citations

"Low-leakage electrostatic discharge..." refers methods in this paper

  • ...The p-type substrate-triggered siliconcontrolled rectifier (SCR) device is used as the main ESD clamping device [6]....

    [...]

Proceedings Article•DOI•
Evaluation of SCR-Based ESD Protection Devices in 90nm and 65nm CMOS Technologies

[...]

J. Di Sarro1, K. Chatty1, R. Gauthier1, Elyse Rosenbaum1•
University of Illinois at Urbana–Champaign1
01 Apr 2007
TL;DR: In this article, the authors compare a number of promising SCR-based ESD protection devices in 90nm and 65nm CMOS technologies implemented with a consistent layout, using ESD metrics such as trigger voltage and current, on-resistance, failure current, turn-on time and DC leakage current.
Abstract: The authors compare a number of promising SCR-based ESD protection devices in 90nm and 65nm CMOS technologies implemented with a consistent layout. The devices are evaluated using ESD metrics such as trigger voltage and current, on-resistance, failure current, turn-on time and DC leakage current. The authors also report that SCR turn-on time is highly dependent on the amplitude of the applied pulse.

47 citations

"Low-leakage electrostatic discharge..." refers background in this paper

  • ...The turn-on behavior of SCR devices is an important index for ESD protection, which had been evaluated in the literature [8], [9]....

    [...]

Related Papers (5)
Resistor-Less Design of Power-Rail ESD Clamp Circuit in Nanoscale CMOS Technology

[...]

19 Oct 2012-IEEE Transactions on Electron Devices
Chih-Ting Yeh, Ming-Dou Ker
Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale CMOS Technology

[...]

24 Feb 2009-IEEE Journal of Solid-state Circuits
Chang-Tzu Wang, Ming-Dou Ker
On the design of power-rail esd clamp circuit with consideration of gate leakage current in 65-nm low-voltage CMOS process

[...]

24 May 2009
Ming-Dou Ker, Po-Yen Chiu, Fu-Yi Tsai, Yeong-Jar Chang 
Design of 2 $\times$ VDD-Tolerant Power-Rail ESD Clamp Circuit With Consideration of Gate Leakage Current in 65-nm CMOS Technology

[...]

01 Jun 2010-IEEE Transactions on Electron Devices
Chang-Tzu Wang, Ming-Dou Ker
New Low-Leakage Power-Rail ESD Clamp Circuit in a 65-nm Low-Voltage CMOS Process

[...]

01 Sep 2011-IEEE Transactions on Device and Materials Reliability
Ming-Dou Ker, Po-Yen Chiu