Low-leakage SRAM design with dual V/sub t/ transistors
Summary (4 min read)
1. Introduction
- Due to technology scaling, reducing the leakage power dissipation has become one of the most important criteria in the design of VLSI systems.
- In their method, the threshold voltage of the transistors of each cache line is controlled separately by using body biasing.
- Most of them result in hardware overhead and hence increase chip's area and reduce the manufacturing yield.
- Therefore, the leakage power consumption can be reduced by using a high threshold voltage for some transistors.
- This technique has four main advantages over previous techniques: .
2. SRAM Design
- A typical SRAM block, shown in Figure 1 , consists of cell arrays, address decoders, column multiplexers, sense amplifiers, I/O, and a control circuitry.
- The functionality of the control circuit is to generate internal signals of the SRAM.
- In the following, the functionality and design of other components are briefly discussed.
A. SRAM Cell
- The bit value stored in the cell is preserved as long as the cell is connected to a supply voltage whose value is greater than the Data Retention Voltage (DRV) [7] .
- This feature, which is due to the presence of cross-coupled inverters inside the 6T SRAM, holds independent of the amount of leakage current.
- There are two dominant leakage paths in a 6T SRAM cell: 1) V dd to ground paths inside the SRAM cell and 2) the bit line to ground paths through the pass transistors.
- To reduce the first type of leakage, the threshold voltages of the pull-down NMOS transistors and/or pull-up PMOS transistors may be increased, whereas to lower the second type of leakage, the threshold voltages of the pull-down NMOS transistors and/or pass transistors can be increased.
B. Cell Array
- Usually there is more than one cell array in an SRAM circuit.
- The size of the cell array depends on both performance and density requirements.
- Generally speaking, as technology shrinks, cell arrays are moving from tall to wide structures [2, 13] .
- Since using wider arrays needs more circuitry for column multiplexers and sense amplifiers, in cases where a large area overhead is intolerable (e.g., large L3 caches), the number of rows can be still high [8, 9] .
D. Column Multiplexers and Sense Amplifiers
- Column multiplexing is inevitable in most SRAM designs because it reduces the number of rows in the cell array and as a result increases the speed.
- Since bit or bit-bar line is discharged about 200mV during a read operation, a sense amplifier is used to sense a small voltage difference and generate a digital value.
3. Hybrid Cell SRAM
- Due to the non-zero delay of the interconnects of the address decoder, word-lines, bit-lines, and the column multiplexer, read and write delay of cells in an SRAM block are different.
- Simulations show that for a typical SRAM block, the read time of the closest cell to the address decoder and the column multiplexer is 5-10% less than that for the furthest cell.
- On the other hand, due to the delay of sense amplifiers and output buffers in a read path, the write delay of a cell is lower than its read delay.
- Considering the fact that increasing the threshold voltage of the PMOS transistors in a 6T SRAM cell increases the write delay, without having much effect on its read delay, one may try to reduce the leakage power by increasing the threshold voltage of the PMOS transistors as long as the write time is below some target value.
- At the same time, there are studies that show the benefit of having more than two threshold voltages is small [11] .
A. SRAM Cell Configurations
- If the threshold voltage of all transistors within a cell is increased, the leakage reduction is the highest; however, since this scenario has the worst effect on the read delay of the cell, the number of cells that can be replaced is low.
- Unlike [3] , the authors use a symmetric cell configuration, which means the symmetric transistors within a cell have the same threshold voltages.
- The configuration ordering is such that, excluding C0 which is the original configuration, the leakage current saving of other configurations is monotonically decreasing as the authors move from C1 toward C7.
- The numbers in Figure 4 and the following ones are obtained using a 180nm CMOS technology with 1.8V for the supply voltage and 0.37V for the low threshold voltage at 100 0 C. Each of these configurations has different effects on read and write delays of cells.
- It can be seen that the increase in read delay for some configurations (e.g., C1 and C3) is very high, whereas it is very small for some other configurations (e.g., C6).
B. Noise Margin
- SRAM cells are especially sensitive to noise during a read operation because the "0" storage node rises to a voltage higher than ground due to a voltage division along the pull-down NMOS transistor and the pass transistor; if this voltage is high enough, it can change the cell's value.
- In general, it is expected that by using high threshold transistors in the SRAM cells, the static noise margin would increase.
- The authors measure the SNM of each configuration under two scenarios: nominal condition and process variation.
B.1 Static Noise Margin under Nominal Conditions
- Simulation results shown in Figure 7 confirm that for all configurations except C6 (i.e., when only PMOS transistors are high threshold), the nominal SNM is more than that of C0 and improves with increasing the high threshold voltage.
- In C6, however, the SNM is slightly less than that of C0 and degrades with increasing the high threshold voltage.
B.2 Static Noise Margin under Process Variation
- Technology scaling has made the process variation one of the concerns of designers.
- As the minimum size transistors are typically used in SRAM cells to achieve a compact design [2] , SRAMs are very sensitive to process variation.
- To measure the static noise margin of each configuration under process variation, the authors used the Monte Carlo simulation technique.
- For each configuration the authors used 400 vectors of six threshold voltages, where each threshold voltage has a Gaussian distribution with its mean equal to the nominal value and its 3σ/µ equal to 0.15.
- The mean and standard deviation of SNM for different configurations are shown in Table 2 .
C. Hybrid Cell Assignment
- To design a hybrid-cell SRAM, the authors need to find out the slowest read and write delay starting with all low-V t SRAM cells (C0 case.) rownum and colnum are the number of rows and columns of the SRAM, respectively.
- In the pseudocode, flag[config][col, row] is a flag that specifies if cell[col,.row] can work with configuration config.
- To speed up the process, instead of checking for possible replacement on each single SRAM cell, one can select n×n blocks and do the checking for the slowest cell in the block.
4. Simulation Results
- To study the efficiency of the proposed technique, a 400MHz, 64Kb SRAM with a 64-bit word has been designed and simulated using Cadence UltraSim in 180nm CMOS technology with 1.8V for the supply voltage and 0.37V for the low threshold voltage.
- For optimizing the delay of the decoder, the predecoding scheme has been used as described in Section III.
- Table 3 shows the leakage power reduction achieved and the utilization of each configuration in the lowleakage SRAM for different values of the high threshold voltage.
- By observing the fact that C3, C5, and C7 are dominated by other configurations, they may be deleted from the set of candidate configurations, resulting in five configurations: C0, C1, C2, C4, and C6.
- From this Table it can be seen that even when using only three configurations, the power reduction is high.
5. Conclusions
- In this paper the authors presented a novel technique for lowleakage SRAM design.
- The authors technique is based on the fact that due to the non-zero delay of interconnects of the address decoder, word-line, bit-line and the column multiplexer, cells of an SRAM have different access delays; thus, the threshold voltage of some transistors of cells can be increased without degrading the performance.
- By using eight different configurations for the SRAM cells, the authors have achieved a low-leakage SRAM without scarifying performance and area.
- Moreover, the simulations have shown that their technique improves the static noise margin under process variation.
- By applying this technique to a 64Kb SRAM, the authors have achieved more than 35% reduction in the leakage-power dissipation.
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Citations
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Cites background from "Low-leakage SRAM design with dual V..."
...Since SRAM cache memories represent a majority of the chip area in current processors [30], [ 35 ], they represent a significant portion of a processor’s power budget due to leakage power and are an active research area, e.g., [34]‐[37]....
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69 citations
Cites methods from "Low-leakage SRAM design with dual V..."
...The idea is to deploy different configurations of six-transistor (6T) SRAM cells corresponding to different threshold voltage and oxide thickness assignments for the transistors [18], [ 19 ]....
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16 citations
Cites background or methods from "Low-leakage SRAM design with dual V..."
...Among different low power design techniques, we first consider the dual-Vt case as it offers no area overhead, and the assignment can be done to avoid any delay overhead [1]....
[...]
...In [1] authors focus on cells with symmetric Vt assignments, while [10] proposes 3 asymmetric configurations....
[...]
...In [1], the authors provide additional analysis that helps decide on the values for the high and low threshold voltages....
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...We focus on the dual-Vt configurations of SRAM cell proposed in [1] and [10]....
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...Some of the low leakage SRAM design techniques are based on using dual threshold voltage assignment [1], [10], or using forward bodybiasing [3], or using sleep transistors [9]....
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15 citations
Cites methods from "Low-leakage SRAM design with dual V..."
...They exploited the error tolerance of MPEG decoding to integrate 8T and 6T SRAM cells for the MSBs and LSBs respectively [14]....
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References
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Frequently Asked Questions (16)
Q2. Why is leakage power dissipation so important?
Due to technology scaling, reducing the leakage power dissipation has become one of the most important criteria in the design of VLSI systems.
Q3. What are the dominant leakage paths in a 6T SRAM cell?
There are two dominant leakage paths in a 6T SRAM cell: 1) Vdd to ground paths inside the SRAM cell and 2) the bit line to ground paths through the pass transistors.
Q4. Why is column multiplexing inevitable in SRAM designs?
Column multiplexing is inevitable in most SRAM designs because it reduces the number of rows in the cell array and as a result increases the speed.
Q5. How many rows can be used in an SRAM array?
since using wider arrays needs more circuitry for column multiplexers and sense amplifiers, in cases where a large area overhead is intolerable (e.g., large L3 caches), the number of rows can be still high [8, 9].
Q6. How can one increase the threshold voltage of all or some of the transistors of a cell?
To reduce the leakage power consumption of a cell, the threshold voltage of all or some of the transistors of the cell can be increased.
Q7. What is the effect of increasing the threshold voltage of the PMOS transistors on the leakage?
Considering the fact that increasing the threshold voltage of the PMOS transistors in a 6T SRAM cell increases the write delay, without having much effect on its read delay, one may try to reduce the leakage power by increasing the threshold voltage of the PMOS transistors as long as the write time is below some target value.
Q8. What is the static noise margin of a CMOS SRAM cell?
The static noise margin (SNM) of a CMOS SRAM cell is defined as the minimum DC noise voltage necessary to flip the state of a cell [12].
Q9. How do the authors achieve a low-leakage SRAM without scarifying performance and area?
By using eight different configurations for the SRAM cells, the authors have achieved a low-leakage SRAM without scarifying performance and area.
Q10. What is the way to reduce leakage power in a SRAM cell?
If the threshold voltage of all transistors within a cell is increased, the leakage reduction is the highest; however, since this scenario has the worst effect on the read delay of the cell, the number of cells that can be replaced is low.
Q11. What is the threshold voltage of the PMOS transistors in a SRAM cell?
Here it is assumed that the threshold voltage of each transistor in the SRAM cell can be adjusted independent of other threshold voltages by changing the channel doping, which is deemed to be a safe assumption because in an SRAM cell the channels of the transistors are not too close to each other [14].
Q12. Why is the delay of the cell array different?
Due to the non-zero delay of the interconnects of the address decoder, word-lines, bit-lines, and the column multiplexer, read and write delay of cells in an SRAM block are different.
Q13. What are the main reasons for the low leakage power in SRAMs?
Although many techniques have been proposed to address the problem of low-leakage SRAM design, most of them result in hardware overhead and hence increase chip’s area and reduce the manufacturing yield.
Q14. What are the advantages of using non-identical cells?
as the authors shall demonstrate later, by using non-identical cells, yet with the same layout footprint, one can realize more power efficient designs.
Q15. What is the difference between a bit and a bit bar line?
Since bit or bit-bar line is discharged about 200mV during a read operation, a sense amplifier is used to sense a small voltage difference and generate a digital value.
Q16. Why does the 6T SRAM have a leakage characteristic?
This feature, which is due to the presence of cross-coupled inverters inside the 6T SRAM, holds independent of the amount of leakage current.