Low power and area efficient error tolerant adder for image processing application
26 Jan 2020-International Journal of Circuit Theory and Applications (John Wiley & Sons, Ltd)-Vol. 48, Iss: 5, pp 696-708
TL;DR: A novel 1‐bit imprecise full adder (IFA) is proposed with less gate count and a new performance metric namely power and error product (PEP) is presented in order to evaluate the approximate adders in terms of power anderror metrics.
About: This article is published in International Journal of Circuit Theory and Applications.The article was published on 2020-01-26. It has received 10 citations till now. The article focuses on the topics: Adder & Image processing.
Citations
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TL;DR: A novel methodology to implement and synthesize different adders (non-speculative and speculative) for any ASIC-based system is proposed and the proposed hybrid Han-Carlson and Kogge-stone speculative adders show improved performance over the state-of-the-art approximate adders.
Abstract: Approximate computing is gaining grip as a computing paradigm for computer vision, data analytics, and image/signal processing applications. In the era of real-time applications, approximate computing plays a significant role. In many computers including digital signal processors (DSP) and a microprocessor, adders are the main element for the implementation of signal processing applications and digital circuit design. The major problem for addition is the propagation delay in the carry chain. As the bit length of the input operand increases, the length of the carry chain increases. To address the carry propagation problem in digital systems, the most efficient adder architectures for VLSI implementation are classified as a parallel prefix adder (PPA) structure. In this paper, a novel methodology to implement and synthesize different adders (non-speculative and speculative) for any ASIC-based system is proposed. The proposed hybrid Han-Carlson and Kogge-stone speculative adders show improved performance (low power and delay) over the state-of-the-art approximate adders. If the approximation fails, then the proposed efficient error correction technique is activated. The proposed speculative H_C adder results in a 23.79% speed improvement over the proposed K_S adder, and 23.86% of energy is saved. The proposed architectures were synthesized for an operand bit length of 16 bits. Finally, the proposed adder is validated for an error-tolerant image processing application resulting in 41.2 dB PSNR.
12 citations
TL;DR: The FOM simulation results indicate that the proposed imprecise multipliers make a significant trade‐off between hardware efficiency and quality for approximate‐computing applications dealing with image multiplication.
12 citations
Cites background from "Low power and area efficient error ..."
...approximate computing has been introduced.(3,4) In the realm of the VLSI universe, approximate computing has become a hotspot in a diverse range of applications, where the computation preciseness takes second place after energy consumption....
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TL;DR: The proposed 16‐bit approximate carry select adder (CSLA) shows a significant reduction of 58% in area delay product and 70% in power delay product, in comparison with the conventional CSLA, and the image metrics results validate that the proposed adder with highest peak signal‐to‐noise ratio is highly adoptable for image processing applications.
7 citations
TL;DR: The results indicate that the power consumption and delay of the proposed approximate floating-point adder have been decreased by 37% and 62% compared with the IEEE‐754 single‐precision floating‐point (FP) adder.
5 citations
3 citations
References
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TL;DR: A survey of techniques for approximate computing (AC), which discusses strategies for finding approximable program portions and monitoring output quality, techniques for using AC in different processing units, processor components, memory technologies, and so forth, as well as programming frameworks for AC.
Abstract: Approximate computing trades off computation quality with effort expended, and as rising performance demands confront plateauing resource budgets, approximate computing has become not merely attractive, but even imperative. In this article, we present a survey of techniques for approximate computing (AC). We discuss strategies for finding approximable program portions and monitoring output quality, techniques for using AC in different processing units (e.g., CPU, GPU, and FPGA), processor components, memory technologies, and so forth, as well as programming frameworks for AC. We classify these techniques based on several key characteristics to emphasize their similarities and differences. The aim of this article is to provide insights to researchers into working of AC techniques and inspire more efforts in this area to make AC the mainstream computing approach in future systems.
890 citations
Additional excerpts
...DESIGNS ADDERS MULTIPLEXERS Adder No of adder Total gates per Total gates No of Gates per Total gates Total gates Type block adder block (1) mux mux (2) (1+2) Conv CSLA FA 28 13 364 15 4 60 424 ET_ CSLA12 AFA 28 6 168 15 4 60 228 SAET_ CSLA12 ACC FA 16 13 208 15 4 60 340 INACC AFA 12 6 72 HSETA15 ACC FA 16 13 208 10 4 40 312 INACC MFA 8 8 64 HPETA14 ACC FA 12 13 156 5 4 20 224 INACC MBAFA 8 6 48 LETA ACC LCSLA 8 11 88 - 148 INACC MFA,MHA 7,1 8,4 56,4 ILETA ACC LCSLA 8 11 88 - 128 INACC IFA 8 5 40...
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TL;DR: This paper proposes logic complexity reduction at the transistor level as an alternative approach to take advantage of the relaxation of numerical accuracy, and demonstrates the utility of these approximate adders in two digital signal processing architectures with specific quality constraints.
Abstract: Low power is an imperative requirement for portable multimedia devices employing various signal processing algorithms and architectures. In most multimedia applications, human beings can gather useful information from slightly erroneous outputs. Therefore, we do not need to produce exactly correct numerical outputs. Previous research in this context exploits error resiliency primarily through voltage overscaling, utilizing algorithmic and architectural techniques to mitigate the resulting errors. In this paper, we propose logic complexity reduction at the transistor level as an alternative approach to take advantage of the relaxation of numerical accuracy. We demonstrate this concept by proposing various imprecise or approximate full adder cells with reduced complexity at the transistor level, and utilize them to design approximate multi-bit adders. In addition to the inherent reduction in switched capacitance, our techniques result in significantly shorter critical paths, enabling voltage scaling. We design architectures for video and image compression algorithms using the proposed approximate arithmetic units and evaluate them to demonstrate the efficacy of our approach. We also derive simple mathematical models for error and power consumption of these approximate adders. Furthermore, we demonstrate the utility of these approximate adders in two digital signal processing architectures (discrete cosine transform and finite impulse response filter) with specific quality constraints. Simulation results indicate up to 69% power savings using the proposed approximate adders, when compared to existing implementations using accurate adders.
637 citations
TL;DR: This paper presents a survey of state-of-the-art work in all aspects of approximate computing and highlights future research challenges in this field.
Abstract: As one of the most promising energy-efficient computing paradigms, approximate computing has gained a lot of research attention in the past few years. This paper presents a survey of state-of-the-art work in all aspects of approximate computing and highlights future research challenges in this field.
420 citations
TL;DR: A novel error-tolerant adder (ETA) is proposed that is able to ease the strict restriction on accuracy, and at the same time achieve tremendous improvements in both the power consumption and speed performance.
Abstract: In modern VLSI technology, the occurrence of all kinds of errors has become inevitable. By adopting an emerging concept in VLSI design and test, error tolerance (ET), a novel error-tolerant adder (ETA) is proposed. The ETA is able to ease the strict restriction on accuracy, and at the same time achieve tremendous improvements in both the power consumption and speed performance. When compared to its conventional counterparts, the proposed ETA is able to attain more than 65% improvement in the Power-Delay Product (PDP). One important potential application of the proposed ETA is in digital signal processing systems that can tolerate certain amount of errors.
286 citations
27 Mar 2017
TL;DR: The EvoApprox8b library provides Verilog, Matlab and C models of all approximate circuits and the error is given for seven different error metrics.
Abstract: Approximate circuits and approximate circuit design methodologies attracted a significant attention of researchers as well as industry in recent years. In order to accelerate the approximate circuit and system design process and to support a fair benchmarking of circuit approximation methods, we propose a library of approximate adders and multipliers called EvoApprox8b. This library contains 430 non-dominated 8-bit approximate adders created from 13 conventional adders and 471 non-dominated 8-bit approximate multipliers created from 6 conventional multipliers. These implementations were evolved by a multi-objective Cartesian genetic programming. The EvoApprox8b library provides Verilog, Matlab and C models of all approximate circuits. In addition to standard circuit parameters, the error is given for seven different error metrics. The EvoApprox8b library is available at: www.fit.vutbr.cz/research/groups/ehw/approxlib
241 citations