Proceedings ArticleDOI
Low Power and Area Efficient Max-log -MAP Decoder
Kalpana Eluri,B. Yamuna,Karthi Balasubramanian,Deepak Mishra +3 more
- pp 431-435
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TLDR
A modified version of the ACS, known as Compare-Add-Select (CSA) has been used in this paper and it is asserted that for the proposed architecture, there is a 50% reduction in both area and power without compromising the performance when compared to the conventional architecture.Abstract:
There is a growing demand for low power error control decoders that are widely used in communication systems. One of the key component in a turbo error control decoder used to decode turbo codes-the Shannon limit approaching code- is a Max-Log-MAP decoder. To scale down the power and area used by the conventional Add-Compare-Select (ACS) module of the Max-Log-MAP decoder, a modified version of the ACS, known as Compare-Add-Select (CSA) has been used in this paper. The scale down is accomplished by reducing the number of operations used in calculating the path metrics of the Max-Log-MAP decoder. The observations assert that for the proposed architecture, there is a 50% reduction in both area and power without compromising the performance when compared to the conventional architecture.read more
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Journal ArticleDOI
Performance Analysis of High Throughput MAP Decoder for Turbo Codes and Self Concatenated Convolutional Codes
TL;DR: VHDL design of Maximum Aposteriori Probability decoder for TC and SECCC, both employing the same constituent code are presented and it is found that SECCC outperforms TC for frame sizes less than or equal to 2048 bits, when invoking a parallelism of 16, 32 and 64.
Book ChapterDOI
Design and Analysis of a Secure Coded Communication System Using Chaotic Encryption and Turbo Product Code Decoder
TL;DR: In this article, the design and analysis of a secure and reliable communication system accomplished using logistic map-based chaotic encryption and turbo product codes is presented. But the system is simulated using MATLAB and it is shown that the use of encryption for secure communication does not degrade the system performance.
Proceedings ArticleDOI
Realization of Turbo Decoder on Coarse Grained Reconfigurable Architectures
TL;DR: In this article , the authors implemented a turbo decoder on coarse grained reconfigurable architectures (CGRAs), a new class of programmable hardware that amalgamates the advantages of both ASICs and FPGAs.
Proceedings ArticleDOI
Realization of Turbo Decoder on Coarse Grained Reconfigurable Architectures
TL;DR: In this paper , the authors implemented a turbo decoder on coarse grained reconfigurable architectures (CGRAs), a new class of programmable hardware that amalgamates the advantages of both ASICs and FPGAs.
References
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Proceedings ArticleDOI
A parametrizable low-power high-throughput turbo-decoder
TL;DR: A high performance turbo decoder that sustains any interleaving scheme, and its major building blocks, the maximum-a-posteriori decoder and the interleaver, are optimized from architecture to layout level to achieve high-throughput at low-power.
Proceedings ArticleDOI
Low power implementation of a turbo-decoder on programmable architectures
TL;DR: This paper presents a low power implementation of the most sophisticated channel decoding algorithm (Turbo-decoding) on programmable architectures based on voltage scheduling for third generation wireless systems.
Journal ArticleDOI
A Novel Area-Efficient VLSI Architecture for Recursion Computation in LTE Turbo Decoders
Arash Ardakani,Mahdi Shabany +1 more
TL;DR: A novel relation existing between the α metrics is introduced, leading to a novel add-compare-select (ACS) architecture that results in, at most, 18.1% less area compared with the reported designs to date while maintaining the same throughput level.
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