Book•
Low Power Design Methodologies
01 Jan 2009-
TL;DR: The present work focuses on the design of low power circuit technologies for portable video-on-demand in wireless communication using CMOS, and the development of algorithms and architectural level methodologies for this purpose.
Abstract: Preface. 1. Introduction J.M. Rabaey, et al. Part I: Technology and circuit design levels. 2. Device and technology impact on low power electronics Chenming Hu. 3. Low power circuit technologies C. Svensson, Dake Liu. 4. Energy-recovery CMOS W.C. Athas. 5. Low power clock distribution J.G. Xi, W.W.-M. Dai. Part II: Logic and module design levels. 6. Logic synthesis and module design levels M. Pedram. 7. Low power arithmetic components T.K. Callawy, E.E. Schwartzlander. 8. Low power memory design K. Itoh. Part III: Architecture and system design levels. 9. Low-power microprocessor design S. Gary. 10. Portable video-on-demand in wireless communication T.H. Meng, et al. 11. Algorithm and architectural level methodologies R. Mehra, et al. Index.
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11 Jun 2001
TL;DR: The experimental results demonstrate that by using only a subset of sensor nodes at each moment, the system achieves a significant energy savings while fully preserving coverage.
Abstract: Wireless sensor networks have emerged recently as an effective way of monitoring remote or inhospitable physical environments. One of the major challenges in devising such networks lies in the constrained energy and computational resources available to sensor nodes. These constraints must be taken into account at all levels of the system hierarchy. The deployment of sensor nodes is the first step in establishing a sensor network. Since sensor networks contain a large number of sensor nodes, the nodes must be deployed in clusters, where the location of each particular node cannot be fully guaranteed a priori. Therefore, the number of nodes that must be deployed in order to completely cover the whole monitored area is often higher than if a deterministic procedure were used. In networks with stochastically placed nodes, activating only the necessary number of sensor nodes at any particular moment can save energy. We introduce a heuristic that selects mutually exclusive sets of sensor nodes, where the members of each of those sets together completely cover the monitored area. The intervals of activity are the same for all sets, and only one of the sets is active at any time. The experimental results demonstrate that by using only a subset of sensor nodes at each moment, we achieve a significant energy savings while fully preserving coverage.
1,074Â citations
10 Aug 1998
TL;DR: A model of dynamically variable voltage processors and basic theorems for power-delay optimization and a static voltage scheduling problem is proposed and formulated as an integer linear programming (ILP) problem.
Abstract: This paper presents a model of dynamically variable voltage processors and basic theorems for power-delay optimization. A static voltage scheduling problem is also proposed and formulated as an integer linear programming (ILP) problem. In the problem, we assume that a core processor can vary its supply voltage dynamically, but can use only a single voltage level at a time. For a given application program and a dynamically variable voltage processor, a voltage scheduling which minimizes energy consumption under an execution time constraint can be found.
826Â citations
TL;DR: An in-depth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems is presented and the many issues facing designers at architectural, logical, and physical levels of design abstraction are described.
Abstract: Low power has emerged as a principal theme in today's electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an in-depth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems and describes the many issues facing designers at architectural, logical, and physical levels of design abstraction. It reviews some of the techniques and tools that have been proposed to overcome these difficulties and outlines the future challenges that must be met to design low power, high performance systems.
550Â citations
Cites background from "Low Power Design Methodologies"
...It is worthwhile to enumerate the major challenges that we believe have to be addressed if we want to keep power dissipation within bounds in the future generations of digital integrated circuits [Rabaey and Pedram 1996]....
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01 Jun 2000
TL;DR: This paper uses the use of SimplePower to evaluate the impact of a new selective gated pipeline register optimization, a high-level data transformation and a pow er-conscious post compilation optimization on the datapath, memory and on-chip bus energy, respectively.
Abstract: In this paper, we presen t the design and use of a comprehensiv e framework, SimplePower, for ev aluating the effect of high-level algorithmic, architectural, and compilation trade-offs on energy. An execution-driven, cycle-accurate RT lev el energy estimation tool that uses transition sensitive energy models forms the cornerstone of this framework. SimplePower also pro vides the energy consumed in the memory system and on-chip buses using analytical energy models.We presen t the use of SimplePower to evaluate the impact of a new selective gated pipeline register optimization, a high-level data transformation and a pow er-conscious post compilation optimization (register relabeling) on the datapath, memory and on-chip bus energy, respectively. We find that these three optimizations reduce the energy by 18-36% in the datapath, 62% in the memory system and 12% in the instruction cache data bus, respectively.
495Â citations
Cites methods from "Low Power Design Methodologies"
...This is in con trast to approaches that rely on information theoretic measures of activity to estimate pow er [12; 16]....
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TL;DR: A finite-state, abstract system model for power-managed systems based on Markov decision processes is introduced and the problem of finding policies that optimally tradeoff performance for power can be cast as a stochastic optimization problem and solved exactly and efficiently.
Abstract: Dynamic power management schemes (also called policies) reduce the power consumption of complex electronic systems by trading off performance for power in a controlled fashion, taking system workload into account. In a power-managed system it is possible to set components into different states, each characterized by performance and power consumption levels. The main function of a power management policy is to decide when to perform component state transitions and which transition should be performed, depending on system history, workload, and performance constraints. In the past, power management policies have been formulated heuristically. The main contribution of this paper is to introduce a finite-state, abstract system model for power-managed systems based on Markov decision processes. Under this model, the problem of finding policies that optimally tradeoff performance for power can be cast as a stochastic optimization problem and solved exactly and efficiently. The applicability and generality of the approach are assessed by formulating the Markov model and optimizing power management policies for several systems.
459Â citations
Cites background from "Low Power Design Methodologies"
...Example 5.1: Consider the following time-stamped request trace, represented as an array of request arrival times (in ms): [ 2 , 5, 6, 7, 12]....
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