Low-power logic styles: CMOS versus pass-transistor logic
Citations
2,848 citations
454 citations
Cites background or methods from "Low-power logic styles: CMOS versus..."
...But, it is shown, through simulation, that CPL is better than CMOS for the studied circuit conditions [7]....
[...]
...5) The CMOS full adder (CMOS) [7] has 28 transistors and is based on the regular CMOS structure (pull-up and pull-down networks)....
[...]
...The complementary CMOS logic adder (CPL) [7]....
[...]
...The disadvantage is that it may not be suitable for VLSI circuits with low voltage supply, as the incomplete voltage swing is not desirable in such circuits [7]....
[...]
...The conventional CMOS adder (CMOS) [7]....
[...]
399 citations
Cites background from "Low-power logic styles: CMOS versus..."
...One example of such design is the standard static CMOS full adder [3]....
[...]
349 citations
Cites background from "Low-power logic styles: CMOS versus..."
...At the circuit design level, considerable potential for optimizing the power-delay product of the multiplier exists by voltage scaling and through the use of contemporary and new CMOS logic styles for the implementation of its embraced combinational circuits [13]–[15], [19]....
[...]
344 citations
Cites background or methods from "Low-power logic styles: CMOS versus..."
...Thus, CPL adder is considered to be able to perform better than C-CMOS adder in [12]....
[...]
...This circuit has inherited the advantages of complementary CMOS logic style, which has been proven in [12] to be superior...
[...]
...The basic difference between the pass-transistor logic and the complementary CMOS logic styles is that the source side of the pass logic transistor network is connected to some input signals instead of the power lines [12], [13]....
[...]
...Several variants of static CMOS logic styles have been used to implement low-power 1-b adder cells [5], [10]–[12]....
[...]
References
1,348 citations
1,024 citations
"Low-power logic styles: CMOS versus..." refers background or methods in this paper
...in the literature [1], [12]–[14], [19]–[23]....
[...]
...With the exception of some very special circuit applications, dynamic logic is no viable candidate for low-power circuit design [1], [8], [9] and was therefore not considered any further in this study....
[...]
...1) Complementary pass-transistor logic (CPL): A CPL gate [1], [13] consists of two NMOS logic networks (one for each sig3Note that each logic function can be realized in a multiplexer structure, but often at a lower circuit efficiency....
[...]
...INTRODUCTION HE increasing demand for low-power very large scale integration (VLSI) can be addressed at different design levels, such as the architectural, circuit, layout, and the process technology level [1]....
[...]
...4(p)], the often used 40-transistor version [1], a version using branch-based gates [26], and a pure pass-gate version [25]....
[...]
654 citations
"Low-power logic styles: CMOS versus..." refers background in this paper
..., low-power synthesis and cell-based design—, also and particularly in the future [10]....
[...]
...5 ( , [10]), and this ratio will decrease even further in deep-submicron technologies, where the carrier drift velocities in NMOS and PMOS transistors become almost equal due to velocity saturation [11]....
[...]
580 citations
485 citations