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Journal ArticleDOI

Low-power logic styles: CMOS versus pass-transistor logic

01 Jul 1997-IEEE Journal of Solid-state Circuits (IEEE)-Vol. 32, Iss: 7, pp 1079-1090
TL;DR: This paper shows that complementary CMOS is the logic style of choice for the implementation of arbitrary combinational circuits if low voltage, low power, and small power-delay products are of concern.
Abstract: Recently reported logic style comparisons based on full-adder circuits claimed complementary pass-transistor logic (CPL) to be much more power-efficient than complementary CMOS. However, new comparisons performed on more efficient CMOS circuit realizations and a wider range of different logic cells, as well as the use of realistic circuit arrangements demonstrate CMOS to be superior to CPL in most cases with respect to speed, area, power dissipation, and power-delay products. An implemented 32-b adder using complementary CMOS has a power-delay product of less than half that of the CPL version. Robustness with respect to voltage scaling and transistor sizing, as well as generality and ease-of-use, are additional advantages of CMOS logic gates, especially when cell-based design and logic synthesis are targeted. This paper shows that complementary CMOS is the logic style of choice for the implementation of arbitrary combinational circuits if low voltage, low power, and small power-delay products are of concern.

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Citations
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Proceedings ArticleDOI
01 May 2000
TL;DR: Wattch is presented, a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level and opens up the field of power-efficient computing to a wider range of researchers by providing a power evaluation methodology within the portable and familiar SimpleScalar framework.
Abstract: Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most existing power analysis tools achieve high accuracy by calculating power estimates for designs only after layout or floorplanning are complete. In addition to being available only late in the design process, such tools are often quite slow, which compounds the difficulty of running them for a large space of design possibilities.This paper presents Wattch, a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level. Wattch is 1000X or more faster than existing layout-level power tools, and yet maintains accuracy within 10% of their estimates as verified using industry tools on leading-edge designs. This paper presents several validations of Wattch's accuracy. In addition, we present three examples that demonstrate how architects or compiler writers might use Wattch to evaluate power consumption in their design process.We see Wattch as a complement to existing lower-level tools; it allows architects to explore and cull the design space early on, using faster, higher-level tools. It also opens up the field of power-efficient computing to a wider range of researchers by providing a power evaluation methodology within the portable and familiar SimpleScalar framework.

2,848 citations

Journal ArticleDOI
TL;DR: A performance analysis of 1-bit full-adder cell is presented, after the adder cell is anatomized into smaller modules, and several designs of each of them are developed, prototyped, simulated and analyzed.
Abstract: A performance analysis of 1-bit full-adder cell is presented. The adder cell is anatomized into smaller modules. The modules are studied and evaluated extensively. Several designs of each of them are developed, prototyped, simulated and analyzed. Twenty different 1-bit full-adder cells are constructed (most of them are novel circuits) by connecting combinations of different designs of these modules. Each of these cells exhibits different power consumption, speed, area, and driving capability figures. Two realistic circuit structures that include adder cells are used for simulation. A library of full-adder cells is developed and presented to the circuit designers to pick the full-adder cell that satisfies their specific applications.

454 citations


Cites background or methods from "Low-power logic styles: CMOS versus..."

  • ...But, it is shown, through simulation, that CPL is better than CMOS for the studied circuit conditions [7]....

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  • ...5) The CMOS full adder (CMOS) [7] has 28 transistors and is based on the regular CMOS structure (pull-up and pull-down networks)....

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  • ...The complementary CMOS logic adder (CPL) [7]....

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  • ...The disadvantage is that it may not be suitable for VLSI circuits with low voltage supply, as the incomplete voltage swing is not desirable in such circuits [7]....

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  • ...The conventional CMOS adder (CMOS) [7]....

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Journal ArticleDOI
TL;DR: The proposed full adder is energy efficient and outperforms several standard full adders without trading off driving capability and reliability and is based on a novel xor-xnor circuit that generates xor and xnor full-swing outputs simultaneously.
Abstract: We present a new design for a 1-b full adder featuring hybrid-CMOS design style. The quest to achieve a good-drivability, noise-robustness, and low-energy operations for deep submicrometer guided our research to explore hybrid-CMOS style design. Hybrid-CMOS design style utilizes various CMOS logic style circuits to build new full adders with desired performance. This provides the designer a higher degree of design freedom to target a wide range of applications, thus significantly reducing design efforts. We also classify hybrid-CMOS full adders into three broad categories based upon their structure. Using this categorization, many full-adder designs can be conceived. We will present a new full-adder design belonging to one of the proposed categories. The new full adder is based on a novel xor-xnor circuit that generates xor and xnor full-swing outputs simultaneously. This circuit outperforms its counterparts showing 5%-37% improvement in the power-delay product (PDP). A novel hybrid-CMOS output stage that exploits the simultaneous xor-xnor signals is also proposed. This output stage provides good driving capability enabling cascading of adders without the need of buffer insertion between cascaded stages. There is approximately a 40% reduction in PDP when compared to its best counterpart. During our experimentations, we found out that many of the previously reported adders suffered from the problems of low swing and high noise when operated at low supply voltages. The proposed full adder is energy efficient and outperforms several standard full adders without trading off driving capability and reliability. The new full-adder circuit successfully operates at low voltages with excellent signal integrity and driving capability. To evaluate the performance of the new full adder in a real circuit, we embedded it in a 4- and 8-b, 4-operand carry-save array adder with final carry-propagate adder. The new adder displayed better performance as compared to the standard full adders

399 citations


Cites background from "Low-power logic styles: CMOS versus..."

  • ...One example of such design is the standard static CMOS full adder [3]....

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Journal ArticleDOI
TL;DR: Simulation results show that the 4- 2 compressor with the proposed XOR-XNOR module and the new fast 5-2 compressor architecture are able to function at supply voltage as low as 0.6 V, and outperform many other architectures including the classical CMOS logic compressors and variants of compressors constructed with various combinations of recently reported superior low-power logic cells.
Abstract: This paper presents several architectures and designs of low-power 4-2 and 5-2 compressors capable of operating at ultra low supply voltages. These compressor architectures are anatomized into their constituent modules and different static logic styles based on the same deep submicrometer CMOS process model are used to realize them. Different configurations of each architecture, which include a number of novel 4-2 and 5-2 compressor designs, are prototyped and simulated to evaluate their performance in speed, power dissipation and power-delay product. The newly developed circuits are based on various configurations of the novel 5-2 compressor architecture with the new carry generator circuit, or existing architectures configured with the proposed circuit for the exclusive OR (XOR) and exclusive NOR ( XNOR) [XOR-XNOR] module. The proposed new circuit for the XOR-XNOR module eliminates the weak logic on the internal nodes of pass transistors with a pair of feedback PMOS-NMOS transistors. Driving capability has been considered in the design as well as in the simulation setup so that these 4-2 and 5-2 compressor cells can operate reliably in any tree structured parallel multiplier at very low supply voltages. Two new simulation environments are created to ensure that the performances reflect the realistic circuit operation in the system to which these cells are integrated. Simulation results show that the 4-2 compressor with the proposed XOR-XNOR module and the new fast 5-2 compressor architecture are able to function at supply voltage as low as 0.6 V, and outperform many other architectures including the classical CMOS logic compressors and variants of compressors constructed with various combinations of recently reported superior low-power logic cells.

349 citations


Cites background from "Low-power logic styles: CMOS versus..."

  • ...At the circuit design level, considerable potential for optimizing the power-delay product of the multiplier exists by voltage scaling and through the use of contemporary and new CMOS logic styles for the implementation of its embraced combinational circuits [13]–[15], [19]....

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Journal ArticleDOI
TL;DR: In this article, the authors investigated the area and power-delay performances of low-voltage full adder cells in different CMOS logic styles for the predominating tree structured arithmetic circuits.
Abstract: The general objective of our work is to investigate the area and power-delay performances of low-voltage full adder cells in different CMOS logic styles for the predominating tree structured arithmetic circuits. A new hybrid style full adder circuit is also presented. The sum and carry generation circuits of the proposed full adder are designed with hybrid logic styles. To operate at ultra-low supply voltage, the pass logic circuit that cogenerates the intermediate XOR and XNOR outputs has been improved to overcome the switching delay problem. As full adders are frequently employed in a tree structured configuration for high-performance arithmetic circuits, a cascaded simulation structure is introduced to evaluate the full adders in a realistic application environment. A systematic and elegant procedure to scale the transistor for minimal power-delay product is proposed. The circuits being studied are optimized for energy efficiency at 0.18-/spl mu/m CMOS process technology. With the proposed simulation environment, it is shown that some survival cells in stand alone operation at low voltage may fail when cascaded in a larger circuit, either due to the lack of drivability or unsatisfactory speed of operation. The proposed hybrid full adder exhibits not only the full swing logic and balanced outputs but also strong output drivability. The increase in the transistor count of its complementary CMOS output stage is compensated by its area efficient layout. Therefore, it remains one of the best contenders for designing large tree structured arithmetic circuits with reduced energy consumption while keeping the increase in area to a minimum.

344 citations


Cites background or methods from "Low-power logic styles: CMOS versus..."

  • ...Thus, CPL adder is considered to be able to perform better than C-CMOS adder in [12]....

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  • ...This circuit has inherited the advantages of complementary CMOS logic style, which has been proven in [12] to be superior...

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  • ...The basic difference between the pass-transistor logic and the complementary CMOS logic styles is that the source side of the pass logic transistor network is connected to some input signals instead of the power lines [12], [13]....

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  • ...Several variants of static CMOS logic styles have been used to implement low-power 1-b adder cells [5], [10]–[12]....

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References
More filters
Book
29 Dec 1995
TL;DR: Digital Integrated Circuits as discussed by the authors is a practical book that bridges the gap between the circuit perspective and system perspective of digital integrated circuit design, including the impact of interconnect, design for low power, issues in timing and clocking, design methodologies and the tremendous effect of design automation on the digital design perspective.
Abstract: Progressive in content and form, this practical book successfully bridges the gap between the circuit perspective and system perspective of digital integrated circuit design. Digital Integrated Circuits maintains a consistent, logical flow of subject matter throughout. Addresses today's most significant and compelling industry topics, including: the impact of interconnect, design for low power, issues in timing and clocking, design methodologies, and the tremendous effect of design automation on the digital design perspective. For readers interested in digital circuit design.

1,348 citations

Book
30 Jun 1995
TL;DR: The Hierarchy of Limits of Power J.D. Stratakos, et al., and Low Power Programmable Computation coauthored with M.B. Srivastava, provide a review of the main approaches to Voltage Scaling Approaches.
Abstract: 1. Introduction. 2. Hierarchy of Limits of Power J.D. Meindl. 3. Sources of Power Consumption. 4. Voltage Scaling Approaches. 5. DC Power Supply Design in Portable Systems coauthored with A.J. Stratakos, et al. 6. Adiabatic Switching L. Svensson. 7. Minimizing Switched Capacitance. 8. Computer Aided Design Tools. 9. A Portable Multimedia Terminal. 10. Low Power Programmable Computation coauthored with M.B. Srivastava. 11. Conclusions. Subject Index.

1,024 citations


"Low-power logic styles: CMOS versus..." refers background or methods in this paper

  • ...in the literature [1], [12]–[14], [19]–[23]....

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  • ...With the exception of some very special circuit applications, dynamic logic is no viable candidate for low-power circuit design [1], [8], [9] and was therefore not considered any further in this study....

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  • ...1) Complementary pass-transistor logic (CPL): A CPL gate [1], [13] consists of two NMOS logic networks (one for each sig3Note that each logic function can be realized in a multiplexer structure, but often at a lower circuit efficiency....

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  • ...INTRODUCTION HE increasing demand for low-power very large scale integration (VLSI) can be addressed at different design levels, such as the architectural, circuit, layout, and the process technology level [1]....

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  • ...4(p)], the often used 40-transistor version [1], a version using branch-based gates [26], and a pure pass-gate version [25]....

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Book
01 Jan 1995
TL;DR: The properties and definitions of Digital ICS are summarized in the partial table of contents.
Abstract: Partial table of contents: Properties and Definitions of Digital ICS. Diodes. Bipolar Junction Transistors. Diode-Transistor Logic (DTL). Schottky Transistor-Transistor (STTL). Other TTL Gates. Basic Emitter-Coupled Logic (ECL). MECL III and ECL 10K. Other ECL Gates. Introduction to MOS Digital Circuits. Resistor Loaded NMOS Inverter. Enhancement-Depletion Loaded NMOS Inverter. NMOS Gates. CMOS Inverter. CMOS Tri-State Gates. CMOS Drivers. Dynamic CMOS. BiCMOS. Latches and Flip-Flops. Semiconductor Read-Only Memories. Direct Coupled NMESFET Logic (DCFL) Inverter. Schottky Diode NMESFET Logic (SDFL) Inverter. Other Gallium Arsenide Logic Family Inverters. Gallium Arsenide NMESFET Gates. Appendices. Supplementary Reading. Selected Answers. Index.

654 citations


"Low-power logic styles: CMOS versus..." refers background in this paper

  • ..., low-power synthesis and cell-based design—, also and particularly in the future [10]....

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  • ...5 ( , [10]), and this ratio will decrease even further in deep-submicron technologies, where the carrier drift velocities in NMOS and PMOS transistors become almost equal due to velocity saturation [11]....

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Journal ArticleDOI
J. Sklansky1
TL;DR: A comparison of several adders shows that, within a set of stated assumptions, conditional-sum addition is superior in certain respects, including processing speed.
Abstract: Conditional-sum addition is a new mechanism for parallel, high-speed addition of digitally-represented numbers. Its design is based on the computation of ``conditional'' sums and carries that result from the assumption of all the possible distributions of carries for various groups of columns. A rapid-sequence mode of operation provides an addition rate that is invariant with the lengths of the summands. Another advantage is the possibility of realizing the adder with ``integrated devices'' or ``modules.'' The logic of conditional-sum addition is applicable to all positive radices, as well as to multisummand operation. In a companion paper, a comparison of several adders shows that, within a set of stated assumptions, conditional-sum addition is superior in certain respects, including processing speed.

580 citations

Journal ArticleDOI
TL;DR: In this article, a complementary pass-transistor logic (CPL) is proposed and applied to almost the entire critical path, which consists of complementary inputs/outputs, an nMOS pass transistor logic network, and CMOS output inverters, and is twice as fast as conventional CMOS due to lower input capacitance and high logic functionality.
Abstract: A 38-ns, 257-mW, 16*16-b CMOS multiplier with a supply voltage of 4 V is described A complementary pass-transistor logic (CPL) is proposed and applied to almost the entire critical path The CPL consists of complementary inputs/outputs, an nMOS pass-transistor logic network, and CMOS output inverters The CPL is twice as fast as conventional CMOS due to lower input capacitance and high logic functionality Its multiplication time is the fastest ever reported, even for bipolar and GaAs ICs, and it can be enhanced further to 26 ns with 60 mW at 77 K >

485 citations