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Proceedings ArticleDOI: 10.1109/COMPSC.2014.7032620

Low power SRAM design using independent gate FinFET at 30nm technology

01 Dec 2014-pp 52-56
Abstract: Energy efficient and low power circuit designing has become challenging for many years Now a day in Modern 1C designing, SRAM design somewhat significant because it will occupy more space on a die and consumes large fraction of energy of the chip Scaling of conventional CMOS circuit leads to have short channel effects due to which, effect such as drain induced barrier lowering, hot electron effect, punch through etc takes place and hence leakage power increases in the transistor In this paper, to minimize short channel effects, we have designed SRAM cell using double gate FinFET FinFET may be the most promising device in the LSI (large scale integration) circuits because it realizes the self-aligned double-gate structure easily Simulation is performed with Cadence virtuoso tool The low power in SRAM is achieved by driving the two gates of FinFET independently We have designed some SRAM circuits using FinFET and compared their results After that, using the best configuration we have designed 8×8 memory array

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Topics: Static random-access memory (53%), Drain-induced barrier lowering (53%), CMOS (52%) ...read more
Citations
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Journal ArticleDOI: 10.1049/IET-CDS.2016.0287
Abstract: Fin field-effect transistors (FinFETs) are replacing the traditional planar metal-oxide-semiconductor FETs (MOSFETs) because of superior capability in controlling short channel effects, leakage current, propagation delay, and power dissipation. Planar MOSFETs face the problem of process variability but the FinFETs mitigate the device-performance variability due to number of dopant ions. This work includes the design of static-random access memory (SRAM) cell using FinFETs. The performance analysis of the ST11T, proposed ST13T SRAM cell, and with power gating sleep transistors is given in this study using the Cadence Virtuoso Tool (V.6.1). Owing to its improved gate controllability and scalability, the FinFET transistor structure is better than the conventional planar complementary MOS technology. The proposed design aims at the power reduction and speed improvement for the SRAM cell. From the result it is clear that optimised proposed FinFET-based ST13T SRAM cell is 92% more power efficient with the use of power gating technique, i.e. sleep transistors approach and having 12.84% less delay due to the use of transmission gates in the access path.

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Topics: Power gating (58%), Low-power electronics (55%), MOSFET (54%) ...read more

13 Citations


Open accessJournal ArticleDOI: 10.17485/IJST/2015/V8I24/79962
Abstract: Power dissipation due to memories has become a major concern of modern digital design. Scaling of CMOS technology has lead to short channel effects. Here CAM cells are designed using FinFET which have better gate control over drain to source current. The CAM cells designed with 30nm LG are used in multi-segment hybrid CAM architecture. The results are compared with the original hybrid CAM. It is observed that the energy metric of proposed architecture is 7% less compared to hybrid CAM.

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2 Citations


Proceedings ArticleDOI: 10.1109/CDAN.2016.7570904
18 Mar 2016-
Abstract: The Scaling of conventional CMOSs (Complementary Metal Oxide Semiconductors) has been facing problems such as short channel effect due to hot electron effect and leakage power. To solve the problems, FinFETs (Fin Field Effect Transistor) device structures are solution. Binary System occupies large area there for the circuit complexity is increasing on a VLSI chip and thus, degrading the performance of binary system. MVL (Multi valued logic) is considered as solution to this issue. In this paper, to minimize short channel effect and reduce circuit complexity on a VLSI chip, we have designed ternary Static Random Access Memory (SRAM) Cell using Shorted Gate FinFET (SG-FinFET). FinFET is double gate transistor architecture to extend scaling over planar device. Two gates have better control over the short channel effects. The paper presents a novel design of 6 Transistor ternary SRAM cell, with separate read and write lines. The proposed SRAM cell designed using Tanner tool version 13 and simulated with the help of W-Edit version 13.

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Topics: Transistor (54%), Hot-carrier injection (53%), Static random-access memory (53%) ...read more

1 Citations

References
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Proceedings ArticleDOI: 10.1109/MTDT.1999.782692
Martin Margala1Institutions (1)
09 Aug 1999-
Abstract: This paper presents an extensive summary of the latest developments in low-power circuit techniques and methods for Static Random Access Memories. The key techniques in power reduction in both active and standby modes are: capacitance reduction by using divided word-line structure or single-bitline cross-point cell activation, pulse operation by using ATD generator and reduced signal swings on high-capacitance predecode lines, write bus lines and datalines, AC current reduction by using multistage decoding, operating voltage reduction coupled with low-power sensing by using charge-transfer amplification, step-down boosted word-line scheme or full current-mode read/write operation and leakage current suppression by using dual-Vt, Auto-Backgate-Controlled multiple-Vt, or dynamic leakage cut-off techniques.

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Topics: Standby power (54%), Cell activation (54%), Circuit design (53%) ...read more

46 Citations


Open accessProceedings ArticleDOI: 10.1109/ISQED.2006.84
27 Mar 2006-
Abstract: This paper presents a method based on dual threshold voltage assignment to reduce the leakage power dissipation of SRAMs while maintaining their performance. The proposed method is based on the observation that the read and write delays of a memory cell in an SRAM block depend on the physical distance of the cell from the sense amplifier and the decoder. The key idea is thus to realize and deploy different types of six-transistor SRAM cells corresponding to different threshold voltage assignments for individual transistors in the cell. Unlike other techniques for low-leakage SRAM design, the proposed technique incurs no area or delay overhead. In addition, it results only in a slight change in the SRAM design flow. Finally, it improves the static noise margin under process variations. Experimental results show that this technique can reduce the leakage-power dissipation of a 64Kb SRAM by more than 35%.

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  • Figure 2. A 6T SRAM cell.
    Figure 2. A 6T SRAM cell.
  • Figure 8. Pseudo-code for the hybrid cell assignment.
    Figure 8. Pseudo-code for the hybrid cell assignment.
  • Table 4. Three suitable configurations for different values of Vt,high
    Table 4. Three suitable configurations for different values of Vt,high
  • Table 5: Power reduction with three and two different configurations
    Table 5: Power reduction with three and two different configurations
  • Figure 9: The approximate floor-planning of the cell array after hybrid cell assignment (a) Vt,high =0.42V (b) Vt,high =0.47
    Figure 9: The approximate floor-planning of the cell array after hybrid cell assignment (a) Vt,high =0.42V (b) Vt,high =0.47
  • + 9

Topics: Sense amplifier (59%), Static random-access memory (57%), Memory cell (53%) ...read more

30 Citations


Proceedings ArticleDOI: 10.1109/ACCT.2013.41
06 Apr 2013-
Abstract: Scaling of conventional CMOS circuit tends to have short channel effects due to which, effect such as drain induced barrier lowering, hot electron effect, punch through etc takes place and hence leakage increases in the transistor. To minimize short channel effects, double gate FinFET is used. FinFET may be the most promising device in the LSI (large scale integration) circuits because it realizes the self-aligned double-gate structure easily. In this paper, six transistors SRAM cell is designed using the tied gate DG FinFET. Sub-threshold leakage current and gate leakage current of internal transistors are observed and compared with the conventional structure of 6T SRAM cell. DG FinFET SRAM cell is applied with self controllable voltage level technique and then leakage current is observed. Simulation is performed with cadence virtuoso tool in 45 nm technology. The total leakage of DG FinFET SRAM cell is reduced by 34% after applying self controllable voltage level technique.

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Topics: Leakage (electronics) (59%), MOSFET (55%), Drain-induced barrier lowering (55%) ...read more

13 Citations


Proceedings ArticleDOI: 10.1109/SMELEC.2008.4770289
01 Nov 2008-
Abstract: CMOS SRAM cell is very less power consuming and have less read and write time. Higher cell ratios can decrease the read and write time and improve stability. PMOS transistor with less width reduces the power consumption. This paper implements 6T SRAM cell with reduced read and write time, area and power consumption. It has been noticed often that increased memory capacity increases the bit-line parasitic capacitance which in turn slows down voltage sensing and make bit-line voltage swings energy expensive. This result in slower and more energy hungry memories.. In this paper Two SRAM cell is being designed for 4 Kb of memory core with supply voltage 1.8 V. A technique of global bit line is used for reducing the power consumption and increasing the memory capacity.

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Topics: Low-power electronics (55%), CMOS (51%)

8 Citations


Proceedings ArticleDOI: 10.1109/ICSICT.2012.6467902
Yuan-Yuan Wang1, Ziou Wang1, Lijun Zhang1Institutions (1)
01 Oct 2012-
Abstract: Power consumption is becoming a pressing issue in cache design. And SRAM (static random access memory) cells occupy a large area of the cache. Recent research shows that SRAM's power dissipation contributes to a key part of the whole chip power consumption. By using separate write and read operation, this paper presents a new 6T-SRAM cell structure of nano-scale technology for low power application. Simulation results with standard 65nm CMOS (complementary metal oxide semiconductor) technology show that the speed is closed to the traditional 6T cell, power consumption is reduced by 22.45% during the write operation of 0. Particularly, in idle mode this structure maintains its data with the help of leakage current and positive feedback, which can greatly improves the power consumption of the nano-scale SRAM.

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Topics: Static random-access memory (58%), Low-power electronics (57%), Cache (56%) ...read more

6 Citations


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