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Proceedings ArticleDOI

Low power vedic multiplier using energy recovery logic

TL;DR: The generation of partial sums and products in a single step in the Vedic approach and the energy recovery capability of the adiabatic logic together realize high speed and low power operation of the design.
Abstract: Multiplier is one of the primary hardware blocks in modern day digital signal processing (DSP) and communication systems. It is extensively used in DSP and image processing applications such as, Fast Fourier Transform (FFT), convolution, correlation, filtering and in ALU of microprocessors. Therefore, high speed, low area and power efficient multiplier design remain the critical factors for the overall system. This paper presents high performance and energy efficient implementation of the binary multiplier. The design is based on ancient Indian Vedic multiplication process and the low power energy recovery (aka adiabatic logic). The generation of partial sums and products in a single step in the Vedic approach and the energy recovery capability of the adiabatic logic together realize high speed and low power operation of the design. A 16X16 Vedic multiplier and conventional array multiplier based on the Differential Cascode Pre-resolve Adiabatic Logic (DCPAL) is proposed in the paper. Simulation results validate this design incurring 87.21 percent lesser power than the standard CMOS equivalent design.
Citations
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Proceedings ArticleDOI
01 Sep 2015
TL;DR: The objective of this paper is to encapsulate an array of applications of Vedic Multiplier in the vast domain of Image processing and Digital signal processing, particularly the different modifications of existing VedicMultiplier architectures enhancing their speed and performance parameters.
Abstract: Rapidly growing technology has raised demands for fast and efficient real time digital signal processing applications. Multiplication is one of the primary arithmetic operations every application demands. A large number of multiplier designs have been developed to enhance their speed. Active research over decades has lead to the emergence of Vedic Multipliers as one of the fastest and low power multiplier over traditional array and booth multipliers. Vedic Multiplier deals with a total of sixteen sutras or algorithms for predominantly logical operations. A large number of them have been proposed using Urdhava Tiryakbhyam sutra rendering them most efficient in terms of speed. The objective of this paper is to encapsulate an array of applications of Vedic Multiplier in the vast domain of Image processing and Digital signal processing, particularly the different modifications of existing Vedic Multiplier architectures enhancing their speed and performance parameters.

9 citations

Proceedings ArticleDOI
01 May 2018
TL;DR: A 4×4 Vedic multiplier utilizing UT sutra in QCA technology is proposed, which are compact and consume less power and is simulated using QCA Designer tool.
Abstract: Multipliers are the major component in most of the processing units and DSP units. Due to the increasing limitations on delay, more importance is given to design of faster multipliers which do fast computations. Research is carried to find new techniques to increase multiplication speed and several modifications have also been made for Wallace tree, Baugh-Wooley and Booth algorithms. Among these multipliers, Vedic multipliers are presently one of the major fields in which research is carried out because they are fast. Urdhva Triyakbhyam (UT) is one among the sixteen Vedic sutras which is significant for multiplication. As power and speed are major concerns in designing multipliers. Quantum dot-Cellular Automata (QCA) is used, which are compact and consume less power. A 4×4 Vedic multiplier utilizing UT sutra in QCA technology is proposed. The design is realized using 2×2 multipliers as basic building blocks and partial product generated by addition using half adders and full adders. The proposed design is simulated using QCA Designer tool.

8 citations

Proceedings ArticleDOI
13 Jul 2015
TL;DR: Simulation results show PFAL is the best technology as compared to CMOS, ECRL design for low power implementation of Vedic multiplier.
Abstract: A multiplier is a vital element in many arithmetic and logical units, digital signal processing and communication system. Therefore speed, area and power consumptions are the critical parameters for the designing of multiplier circuits. This paper presents a comparative study of binary Vedic multiplier using CMOS, PFAL and ECRL. The design is based on ancient Indian Vedic mathematics and the low power charge recovery logic. In Vedic multiplication, generation of partial sums and products is performed in single step so this along with adiabatic approach helps in realizing the high speed and low power operation of the binary Vedic multiplier design. The designs are simulated on Cadence Virtuoso Tool using UMC 180 nm CMOS technology. Simulation results show PFAL is the best technology as compared to CMOS, ECRL design for low power implementation of Vedic multiplier.

8 citations


Cites background from "Low power vedic multiplier using en..."

  • ...This property makes it effective for implementing high performance signal processing applications [3]....

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  • ...This sutra yields fast multiplication by generating partial product and sum terms in a single iteration step [3]....

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  • ...So this approach sums performs addition and multiplication in single step therefore this multiplication scheme is fast [3]....

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Proceedings ArticleDOI
01 Apr 2016
TL;DR: Design of optimized high speed and low power Vedic multiplier based on Vedic sutra Urdhva Tiryagbhyam based on adiabatic logic is presented and its performance is evaluated by comparing it with conventional MOS design.
Abstract: This paper presents design of optimized high speed and low power Vedic multiplier based on Vedic sutra Urdhva Tiryagbhyam. Adiabatic logic is used to reduce the power consumption of Vedic multiplier and its performance is evaluated by comparing it with conventional MOS design. The power consumption of Adiabatic Vedic multiplier is less than power consumed by Vedic multiplier without adiabatic logic is analyzed. The circuit 2×2, 4×4 Vedic multipliers are designed and simulated on 180nm technology using Tanner EDA Tool 13.0.

7 citations

Proceedings ArticleDOI
01 Dec 2015
TL;DR: In this article, the authors studied the performance of various multipliers, including Array multiplier, Wallace tree multiplier, Bypassing multiplier, Modified Booth multiplier, Vedic multiplier and Booth recorded Wallace tree multipliers.
Abstract: In this paper we are going to study Array multiplier, Wallace multiplier, Bypassing multiplier, Modified Booth multiplier, Vedic multiplier and Booth recorded Wallace tree multiplier which have been proposed by different researchers. When the study of the various multipliers have been performed, Array multiplier is found to have the largest delay and large power consumption while Booth encoded Wallace tree multiplier has the least delay though it also have a large area. We also realized that, with proper optimization the performance of the multipliers can be increased significantly, irrespective of the type. Temporal tilling method optimized array multiplier delay and power dissipation is found to increase by 50% and 30% respectively while using the partially guarded technique power consumption is reduced by 10–44% with 30–36% less area overhead. Booth recorded Wallace tree multiplier is found to be 67% faster than the Wallace tree multiplier, 53% faster than the Vedic multiplier, 22% faster than the radix 8 booth multipliers. We also study various optimization techniques for Wallace multiplier, bypassing multiplier, modified booth multiplier and Vedic multiplier.

7 citations


Cites methods or result from "Low power vedic multiplier using en..."

  • ...(2013) [23] shows that the delay of the multiplier can be decreased by 45% and the multiplier architecture suggested by Hardik Sangani et al. (2014) [26] based on Adaibatic logics shows that the power consumption can be reduced by 67% and 57% when compared with when compared with array and Vedic multiplier....

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  • ...Hardik Sangani et al. (2014) [26] proposed a multiplier architecture, based on Vedic multiplication and adiabatic logic....

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  • ...(2013) [23] shows that the delay of the multiplier can be decreased by 45% and the multiplier architecture suggested by Hardik Sangani et al. (2014) [26] based on Adaibatic logics shows that the power consumption can be reduced by 67% and 57% when compared with when compared with array and Vedic…...

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References
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01 Jan 2016
TL;DR: The digital integrated circuits a design perspective is universally compatible with any devices to read, and is available in the digital library an online access to it is set as public so you can get it instantly.
Abstract: Thank you very much for reading digital integrated circuits a design perspective. Maybe you have knowledge that, people have search hundreds times for their favorite readings like this digital integrated circuits a design perspective, but end up in infectious downloads. Rather than reading a good book with a cup of coffee in the afternoon, instead they juggled with some harmful virus inside their computer. digital integrated circuits a design perspective is available in our digital library an online access to it is set as public so you can get it instantly. Our digital library hosts in multiple locations, allowing you to get the most less latency time to download any of our books like this one. Merely said, the digital integrated circuits a design perspective is universally compatible with any devices to read.

602 citations


"Low power vedic multiplier using en..." refers background in this paper

  • ...Of these, the tree and array architecture based multipliers are the two major types employed [1]....

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Journal ArticleDOI
TL;DR: Efficient charge recovery logic (ECRL) is proposed as a candidate for low-energy adiabatic logic circuit and shows four to six times power reduction with a practical loading and operation frequency range.
Abstract: Efficient charge recovery logic (ECRL) is proposed as a candidate for low-energy adiabatic logic circuit. Power comparison with other logic circuits is performed on an inverter chain and a carry lookahead adder (CLA). ECRL CLA is designed as a pipelined structure for obtaining the same throughput as a conventional static CMOS CLA. Proposed logic shows four to six times power reduction with a practical loading and operation frequency range. An inductor-based supply clock generation circuit is proposed. Circuits are designed using 1.0-/spl mu/m CMOS technology with a reduced threshold voltage of 0.2 V.

503 citations

Proceedings ArticleDOI
01 Nov 2008
TL;DR: In this paper, a new multiplier and square architecture is proposed based on algorithm of ancient Indian Vedic Mathematics, for low power and high speed applications, which is based on generating all partial products and their sums in one step.
Abstract: Vedic mathematics is the name given to the ancient Indian system of mathematics that was rediscovered in the early twentieth century from ancient Indian sculptures (Vedas). It mainly deals with Vedic mathematical formulae and their application to various branches of mathematics. The algorithms based on conventional mathematics can be simplified and even optimized by the use of Vedic Sutras. These methods and ideas can be directly applied to trigonometry, plain and spherical geometry, conics, calculus (both differential and integral), and applied mathematics of various kinds. In this paper new multiplier and square architecture is proposed based on algorithm of ancient Indian Vedic Mathematics, for low power and high speed applications. It is based on generating all partial products and their sums in one step. The design implementation on ALTERA Cyclone -II FPGA shows that the proposed Vedic multiplier and square are faster than array multiplier and Booth multiplier.

174 citations

01 Jan 2004
TL;DR: It has been demonstrated that implementing the array and booth multiplier as 4x4 modules in the proposed architecture leads to a considerable improvement in their efficiency.
Abstract: A N X N bit parallel overlay multiplier architecture is designed for high speed DSP operations. The architecture is based on the vertical and crosswise algorithm of ancient Indian Vedic Mathematics. In the proposed architecture grouping of the bits 4 at a time is done for both the multiplicand and multiplier. Thus the whole multiplication operation is decomposed into 4x4 bit multiplication modules. The 4x4 multiplication modules can be implemented by using any multiplier such as array, booth, wallace or future proposed efficient multiplier. It has been demonstrated that implementing the array and booth multiplier as 4x4 modules in the proposed architecture leads to a considerable improvement in their efficiency. Due to its efficient performance, the overlay architecture is a boon for DSP applications such as multimedia and image processing. In order to test the effect of further decomposition of the bits on the efficiency of the architecture, the 4x4 multiply module are further decomposed into parallel 2x2 multiply modules by grouping two bits at a time for both 4 bit multiplicand and multiplier. The results has shown that decomposition nearly reaches a saturation level in its efficiency at 4x4 decomposition and further decomposition has a not a significant improvement in the architecture efficiency .

86 citations


"Low power vedic multiplier using en..." refers background in this paper

  • ...These factors make it unsuitable for low power and high frequency applications [2] [3]....

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Journal ArticleDOI
TL;DR: Differential Cascode Pre-resolving Adiabatic Logic (DCPAL) is presented that can operate with greater functionality, larger fan-in and high energy efficiency, and energy saving against optimized 2N2N2P and PFAL 8-bit multiplier circuits enhances further at higher frequencies.
Abstract: This paper presents Differential Cascode Pre-resolve Adiabatic Logic (DCPAL) that can operate with greater functionality, larger fan-in and high energy efficiency. It is a diode free and dual rail logic operated by four phase power clock for the adiabatic pipeline. Less complex with differential cascode structure and fewer numbers of transistors, the pre-resolving feature for the complementary inputs achieves reduction in latency, significant drop in the switched capacitance that realizes power efficiency, better silicon area efficiency, reduced leakage paths and glitch-free output with reduced switching transients. Energy efficiency against static CMOS equivalent and better speed performance against 2N2P, 2N2N2P, PFAL and IPGL equivalent circuits are proved. By the use of post-layout simulations of multi-bit adder and multiplier circuits adopted through full-custom circuit design, the DCPAL achieves adiabatic gain values in the range of 20.85 at 100 MHz power clock frequency to 9.88 at 500 MHz against the static CMOS equivalent 8-bit Wallace tree multiplier circuit. Energy saving of 50% and 45% is achieved against optimized 2N2N2P and PFAL 8-bit multiplier circuits at 500 MHz, and energy saving against these circuits enhances further at higher frequencies.

33 citations


"Low power vedic multiplier using en..." refers methods in this paper

  • ...DCPAL is a dual rail Preresolve logic designed using nMOS based Differential Cascode Voltage Switch (DCVS) tree structure and pMOS sense-amplifier memory recharge scheme to achieve efficient energy recovery, along with that it has two pull down nodes providing both the function and its complement in the same circuit thereby reducing circuit complexity and improving overall latency [7]....

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  • ...In this paper, we employ Differential Cascode Pre-resolve Adiabatic Logic (DCPAL) for implementing the design [7]....

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