Proceedings ArticleDOI
Low power XOR gate design and its applications
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TLDR
The methodology discussed in this paper, the same design for XOR logic can be made possible with 6 transistors, and this design consumes 50% less power than that of conventional Xor logic design with CMOS technology.Abstract:
With advent of technology scaling, the prime objective of design i.e. low power consumption can be easily acquired. For any digital logic design the power consumption depends on; Supply voltage, number of transistors incorporated in circuit and scaling ratios of the same. As CMOS technology supports inversion logic designs; NAND & NOR structures are useful for converting any logic equation into physical level design that comprises of PMOS and NMOS transistors. In similar way, logic can be implemented in other styles as well, with the difference in number of transistors required. The conventional CMOS design for XOR logic can be possible with 8 or more than 8 transistors, with the methodology discussed in this paper, the same design for XOR logic can be made possible with 6 transistors. The proposed methodology consists of Pass transistor logic and Single feedback topology. This design consumes 50% less power than that of conventional XOR logic design with CMOS technology. Since the design for XOR logic, is useful for variety of applications such as Data encryption, Arithmetic circuits, Binary to Gray encoding etc. the XOR logic has been selected for design. The design explained in this paper is simulated with Cadence 90nm technology.read more
Citations
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Proceedings ArticleDOI
FinFET Variability and Near-threshold operation: Impact on Full Adders design using XOR Blocks
TL;DR: 9 full adders built with internal blocks that contain different combinations of 3 XOR logic circuits operating with nominal and near-threshold voltages under process variability effects are analyzed to design more robust and low power circuits.
Proceedings ArticleDOI
Impact of Near-Threshold and Variability on 7nm FinFET XOR Circuits
TL;DR: Ten different XOR logic gates arrangements behavior at near-threshold operation under process, voltage, and temperature (PVT) variability effects are evaluated to provide valuable data and how the impact of variability is an important factor that must be explored to design more robust circuits.
Proceedings ArticleDOI
A Novel Power Efficient XOR Gate Based on Single Inverted Input
TL;DR: The novel design using only one inverted input is found to be 80.67% optimized for power in comparison to CMOS logic and 59.59% power optimized in comparison with PTL logic.
Proceedings ArticleDOI
Mitigation Effects of Decoupling Cells on Full Adders Process Variability
TL;DR: This work explores decoupling cells on different adder topologies using a 7nm FinFET technology to mitigate variability effects, finding that this technique adoption has a high impact on the results of circuits operating at near-threshold voltage.
Proceedings ArticleDOI
Power Optimization Techniques and Physical Design Flow on Repeaters for High-Speed Processor Core in sub 14nm
TL;DR: This project work major focus is on designing the repeater FuBs (Functional unit Blocks) and detail explanation on timing convergence, power optimization and achieving good quality on the design block is given.
References
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Journal ArticleDOI
Low-power logic styles: CMOS versus pass-transistor logic
R. Zimmermann,Wolfgang Fichtner +1 more
TL;DR: This paper shows that complementary CMOS is the logic style of choice for the implementation of arbitrary combinational circuits if low voltage, low power, and small power-delay products are of concern.
Journal ArticleDOI
New efficient designs for XOR and XNOR functions on the transistor level
TL;DR: In this article, two new methods are proposed to implement the exclusive-OR and exclusive-NOR functions on the transistor level, one uses non-complementary signal inputs and the least number of transistors, while the other one improves the performance of the prior method but two more transistors are utilized.
Journal ArticleDOI
Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gates
TL;DR: This paper proposes a technique to build a total of 41 new 10-transistor full adders using novel XOR and XNOR gates in combination with existing ones to reduce the threshold-voltage loss of the pass transistors.
Journal ArticleDOI
Low-voltage low-power CMOS full adder
TL;DR: In this paper, a formal design procedure for realising a minimal transistor CMOS pass network XOR-XNOR cell, that is fully compensated for threshold voltage drop in MOS transistors, is presented.
Proceedings ArticleDOI
A new design of XOR-XNOR gates for low power application
Nabihah Ahmad,Rezaul Hasan +1 more
TL;DR: A combination of XOR-XNOR gate using 6-transistors for low power applications using 65nm CMOS technology in Cadence environment and results show that the proposed design has lower power dissipation and has a full voltage swing.