Journal ArticleDOI
Low-subthreshold-swing tunnel transistors
Qin Zhang,Wei Zhao,Alan Seabaugh +2 more
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TLDR
In this paper, the subthreshold swing of field effect interband tunnel transistors is not limited to 60 mV/dec as in the MOSFET, but instead is shown to be sub-60 mv/dec.Abstract:
A formula is derived, which shows that the subthreshold swing of field-effect interband tunnel transistors is not limited to 60 mV/dec as in the MOSFET. This formula is consistent with two recent reports of interband tunnel transistors, which show lower than 60-mV/dec subthreshold swings and provides two simple design principles for configuring these transistors. One of these principles suggests placing the gate adjacent to the tunnel junction. Modeling of this configuration verifies that sub-60-mV/dec swing is possible.read more
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Journal ArticleDOI
Electronics based on two-dimensional materials
Gianluca Fiori,Francesco Bonaccorso,Giuseppe Iannaccone,Tomas Palacios,Daniel Neumaier,Alan Seabaugh,Sanjay K. Banerjee,Luigi Colombo +7 more
TL;DR: A review of electronic devices based on two-dimensional materials, outlining their potential as a technological option beyond scaled complementary metal-oxide-semiconductor switches and the performance limits and advantages, when exploited for both digital and analog applications.
Journal ArticleDOI
Tunnel field-effect transistors as energy-efficient electronic switches
Adrian M. Ionescu,Heike Riel +1 more
TL;DR: Tunnels based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal–oxide–semiconductor transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.
Journal ArticleDOI
Vertical field-effect transistor based on graphene?WS2 heterostructures for flexible and transparent electronics
Thanasis Georgiou,Rashid Jalil,Branson D. Belle,L. Britnell,Roman V. Gorbachev,Sergey V. Morozov,Yong-Jin Kim,Yong-Jin Kim,Ali Gholinia,Sarah J. Haigh,Oleg Makarovsky,Laurence Eaves,Laurence Eaves,Leonid Ponomarenko,Andre K. Geim,Konstantin S. Novoselov,Artem Mishchenko +16 more
TL;DR: A new generation of field-effect vertical tunnelling transistors where two-dimensional tungsten disulphide serves as an atomically thin barrier between two layers of either mechanically exfoliated or chemical vapour deposition-grown graphene are described.
Journal ArticleDOI
Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec
TL;DR: In this paper, a 70-nm n-channel tunneling field effect transistor (TFET) with sub-threshold swing (SS) of 52.8 mV/dec at room temperature was demonstrated.
Journal ArticleDOI
Low-Voltage Tunnel Transistors for Beyond CMOS Logic
Alan Seabaugh,Qin Zhang +1 more
TL;DR: This review introduces and summarizes progress in the development of the tunnel field- effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges.
References
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Journal ArticleDOI
Band-to-band tunneling in carbon nanotube field-effect transistors.
TL;DR: How the structure of the nanotube is the key enabler of this particular one-dimensional tunneling effect is discussed, which is controlled here by the valence and conduction band edges in a bandpass-filter-like arrangement.
Journal ArticleDOI
Short-channel effect in fully depleted SOI MOSFETs
TL;DR: In this article, the short channel effect in fully depleted silicon-on-insulator MOSFETs has been studied by a two-dimensional analytical model and by computer simulation, and it is found that the vertical field through the depleted film strongly influences the lateral field across the source and drain regions.
Proceedings ArticleDOI
A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors
Tahir Ghani,Mark Armstrong,C. Auth,M. Bost,P. Charvat,G. Glass,T. Hoffmann,K. Johnson,C. Kenyon,Jason Klaus,B. McIntyre,Kaizad Mistry,Anand Portland Murthy,J. Sandford,M. Silberstein,Swaminathan Sivakumar,Pete Smith,K. Zawadzki,Scott E. Thompson,M. Bohr +19 more
TL;DR: In this article, the authors describe a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers, which features an epitaxially grown strained SiGe film embedded in the source drain regions.
Journal ArticleDOI
Complementary tunneling transistor for low power application
Peng-Fei Wang,K. Hilsenbeck,Th. Nirschl,M. Oswald,Ch. Stepper,M. Weis,Doris Schmitt-Landsiedel,Walter Hansch +7 more
TL;DR: In this paper, the complementary Si-based tunneling transistors are investigated in detail, and it is found that the band-to-band tunneling current is controlled by the gate-tosource voltage.
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