Low-Temperature ICP-CVD SiN x as Gate Dielectric for GaN-Based MIS-HEMTs
TL;DR: SiN x deposited by inductively coupled plasma chemical vapor deposition (ICP-CVD) technique at low temperature (70 °C) was investigated as gate dielectric for AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) as mentioned in this paper.
Abstract: SiN x deposited by inductively coupled plasma chemical vapor deposition (ICP-CVD) technique at low temperature (70 °C) was investigated as gate dielectric for AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) Besides significant reduction in gate leakage current, the MIS-HEMTs showed improvement in drain current characteristics, 2DEG channel mobility, $I_{\mathrm{\scriptscriptstyle ON}}/I_{\mathrm{\scriptscriptstyle OFF}}$ ratio, ON-resistance, and three terminal breakdown voltage as compared with reference HEMTs Very small capacitance–voltage hysteresis (~68 mV) was observed for a gate swing of −10 to +5 V The effect of SiN x thickness ( $t_{\mathrm {SiN}x}$ ) on the characteristics of MIS-HEMTs was studied The performance of fabricated MIS-HEMTs was found to be stable for a wide range of temperature
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TL;DR: In this paper, the gate leakage current in GaN-based high-electron-mobility transistors (MIS-HEMTs) with SiNx as gate dielectric was investigated.
Abstract: Gate leakage mechanisms in AlInN/GaN and AlGaN/GaN metal insulator semiconductor high-electron-mobility transistors (MIS-HEMTs) with SiNx as gate dielectric have been investigated. It is found that the conduction in the reverse gate bias is due to Poole-Frenkel emission for both MIS-HEMTs. The dominant conduction mechanism in low to medium forward bias is trap-assisted tunneling while it is Fowler–Nordheim tunneling at high forward bias. However, conduction near zero gate bias is dominated by defect-assisted tunneling for both sets of MIS-HEMTs. The gate leakage current is primarily dependent on the properties of the gate dielectric material and dielectric/ semiconductor interface rather than the barrier layer. A model is proposed for the gate leakage current in GaN-based MIS-HEMTs, and the method to extract the related model parameters is also presented in this paper. The proposed gate current model matches well with the experimental results for both AlInN/GaN and AlGaN/GaN MIS-HEMTs over a wide range of gate bias and measurement temperature.
40 citations
Cites background or methods from "Low-Temperature ICP-CVD SiN x as Ga..."
...The values of Q P1 and (QI − QSP_GaN − q N it) in (1) and (2) can be extracted from the VTh expressions of HEMT and MIS-HEMT given by [12] and [14]...
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...2723932 The high IG in HEMTs is significantly suppressed in metalinsulator-semiconductor HEMTs (MIS-HEMTs) [12]–[14]....
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...Details of fabrication steps and deposition process of inductively coupled plasma chemical vapor deposition SiNx can be found in [14]....
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TL;DR: In this article, drain current transient spectroscopy (DCTS) and low-frequency (LF) output admittance (Y}_{{22}}$ ) dispersion techniques were used to identify trap locations and types.
Abstract: Deep-level traps in AlGaN/GaN- and AlInN/GaN-based HEMTs with different buffer doping technologies are identified by drain current transient spectroscopy (DCTS) and low-frequency (LF) output admittance ( ${Y}_{{22}}$ ) dispersion techniques. TCAD simulations are also carried out to determine the spatial location and type of traps. The DCTS and LF ${Y}_{{22}}$ measurements on Al0.25Ga0.75N/GaN HEMT (Fe-doped buffer) reveal a single electron trap at ${E}_{C} - {0.47}$ eV. On the other hand, an electron trap at ${E}_{C} -$ (0.53–0.59) eV and a deep hole trap at ${E}_{V} + {0.82}$ eV are detected in Al0.845In0.155N/AlN/GaN HEMT with unintentionally doped (UID) buffer, while a slow detrapping behavior is noticed at ${E}_{C} - {0.6}$ eV in Al0.83In0.17N/AlN/GaN HEMT with C-doped buffer. The DCTS and LF ${Y}_{{22}}$ measurements yield nearly the same trap signatures, indicating the reliability of the trap characterization techniques used in this article. The simulated LF ${Y}_{{22}}$ characteristics show that all these traps are acceptor-like states located in the buffer layer. The identified trap parameters in various buffers may be helpful to improve the crystalline quality of the epitaxial buffer layers.
36 citations
Cites methods from "Low-Temperature ICP-CVD SiN x as Ga..."
...ICP-CVD silicon nitride [38] was used for device surface passivation....
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TL;DR: In this article, device simulation studies of surface and buffer trapping effects on static I-V, output-admittance (Y22), and transient characteristics of AlGaN/GaN HEMTs are described.
Abstract: This paper describes device simulation studies of surface and buffer trapping effects on static I-V, output-admittance (Y22), and transient characteristics of AlGaN/GaN HEMTs. The TCAD simulation model considering surface donors at EC − 0.5 eV and buffer traps at EC − 0.47 eV have been used to quantitatively reproduce the measured DC, Y22 frequency dispersion, gate-lag (GL) and drain-lag (DL) transients of AlGaN/GaN HEMT with 0.25 µm gate length. Moreover, simulated GL and DL transient responses of AlGaN/GaN HEMT with a longer gate length (0.5 µm) are validated with the reported experimental results. The impact of barrier trap at EC − 0.45 eV on the HEMT properties is also explored. It is shown that by matching simulation results with experimental data, it is possible to identify the trap (surface or buffer) responsible for a particular trapping induced degradation as well as its concentration and capture cross-section.
21 citations
TL;DR: In this article, the authors report optimized transport properties in gate recessed enhancementmode GaN MOS-HEMTs by incorporating silicon into atomic layer deposited gate dielectric HfO2.
Abstract: In this letter, we report optimized transport properties in gate recessed enhancement-mode GaN MOS-HEMTs by incorporating silicon into atomic layer deposited gate dielectric HfO2. Compared with commonly used HfO2 gate dielectric, the interface trap density can be reduced by nearly an order of magnitude and the fixed oxide traps inside are reduced to almost half using the high-quality passivation of HfSiO x . The MOS-HEMTs based on HfSiO x exhibit a threshold voltage of 1.5 V, excellent subthreshold swing of 65 mV/dec, and a high on–off ratio of $\textsf {3} \times \textsf {10}^{\textsf {10}}$ . The incorporation of silicon in HfO2 can also increase the dielectric breakdown property with maximum gate electric field of 2.85 MV/cm for a 10-year time-dependent gate dielectric breakdown lifetime, which is 36% higher than pure HfO2. The maximum breakdown voltage of HfSiO x MOS-HEMT is 742 V, which is 30% higher than HfO2 MOS-HEMT.
20 citations
Cites methods from "Low-Temperature ICP-CVD SiN x as Ga..."
...However, HfO2 on GaN MOS-HEMTs suffers from high leakage current because of insufficient barrier height [19], which will deteriorate device performance via gate leakage....
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...To evaluate the reliability of these MOS-HEMTs, three groups of devices were stressed at constant gate-source voltage with source and drain grounded for each MOSHEMT....
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...The reversible breakdown property in ultra-thin dielectrics is not observed in power MOS-HEMTs with thick dielectrics [31]....
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...In conclusion, this letter reports high-κ dielectrics in recessed gate E-mode GaN MOS-HEMTs, and silicon inclusion into HfO2 dielectric provides better passivation in the recess channel region and minimized interface and fixed oxide traps and near-ideal subthreshold slope can be achieved....
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...4(d) shows the off-state breakdown voltage for both E-mode MOS-HEMTs....
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References
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TL;DR: In this article, the authors investigated the role of spontaneous and piezoelectric polarization on the carrier confinement at GaN/AlGaN and AlGaN/GaN interfaces.
Abstract: Carrier concentration profiles of two-dimensional electron gases are investigated in wurtzite, Ga-face AlxGa1−xN/GaN/AlxGa1−xN and N-face GaN/AlxGa1−xN/GaN heterostructures used for the fabrication of field effect transistors. Analysis of the measured electron distributions in heterostructures with AlGaN barrier layers of different Al concentrations (0.15
2,581 citations
TL;DR: In this paper, the authors reported the highest reported microwave power density for undoped sapphire substrated AlGaN/GaN HEMT's on the same wafer.
Abstract: Surface passivation of undoped AlGaN/CaN HEMT's reduces or eliminates the surface effects responsible for limiting both the RF current and breakdown voltages of the devices. Power measurements on a 2/spl times/125/spl times/0.5 /spl mu/m AlGaN/GaN sapphire based HEMT demonstrate an increase in 4 GHz saturated output power from 1.0 W/mm [36% peak power-added efficiency (PAE)] to 2.0 W/mm (46% peak PAE) with 15 V applied to the drain in each case. Breakdown measurement data show a 25% average increase in breakdown voltage for 0.5 /spl mu/m gate length HEMT's on the same wafer. Finally, 4 GHz power sweep data for a 2/spl times/75/spl times/0.4 /spl mu/m AlGaN/GaN HEMT on sapphire processed using the Si/sub 3/N/sub 4/ passivation layer produced 4.0 W/mm saturated output power at 41% PAE (25 V drain bias). This result represents the highest reported microwave power density for undoped sapphire substrated AlGaN/GaN HEMT's.
752 citations
"Low-Temperature ICP-CVD SiN x as Ga..." refers background in this paper
...However, as HEMTs suffer from high leakage current, VBD for HEMT is defined as the VDS when ID exceeds 1 mA/mm [32]....
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TL;DR: A flip-chip amplifier IC using a 4-mm device generated 14 W at 8 GHz, representing the highest CW power obtained from GaN-based integrated circuits to date.
Abstract: Research work focusing on the enhancement of large-signal current-voltage (I-V) capabilities has resulted in significant performance improvement for AlGaN/GaN HEMT's. 100-150 /spl mu/m wide devices grown on SiC substrates demonstrated a record power density of 9.8 W/mm at 8 GHz, which is about ten times higher than GaAs-based FETs; similar devices grown on sapphire substrates showed 6.5 W/mm, which was thermally limited, 2-mm-wide devices flip-chip mounted on to AlN substrates produced 9.2-9.8 W output power at 8 GHz with 44-47% PAE. A flip-chip amplifier IC using a 4-mm device generated 14 W at 8 GHz, representing the highest CW power obtained from GaN-based integrated circuits to date.
527 citations
20 May 2010
TL;DR: In this article, GaN power transistors on Si substrates for power switching application are reported, and current collapse phenomena are discussed for GaN-HFETs on Si substrate, resulting in suppression of the current collapse due to using the conducting Si substrate.
Abstract: In this paper, GaN power transistors on Si substrates for power switching application are reported. GaN heterojunction field-effect transistor (HFET) structure on Si is an important configuration in order to realize a low loss and high power devices as well as one of the cost-effective solutions. Current collapse phenomena are discussed for GaN-HFETs on Si substrate, resulting in suppression of the current collapse due to using the conducting Si substrate. Furthermore, attempts for normally off GaN-FETs were examined. A hybrid metal-oxide-semiconductor HFET structure is a promising candidate for obtaining devices with a lower on-resistance (Ron) and a high breakdown voltage (Vb).
454 citations
01 Jan 2010
TL;DR: A hybrid metal-oxide-semiconductor HFET structure is a promising candidate for obtaining devices with a lower on-resistance and a high breakdown voltage as well as one of the cost-effective solutions.
Abstract: In this paper, GaN power transistors on Si substrates for power switching application are reported. GaN heterojunction field-effect transistor (HFET) structure on Si is an important configuration in order to realize a low loss and high power devices as well as one of the cost-effective solutions. Current collapse phenomena are discussed for GaN-HFETs on Si substrate, resulting in suppression of the current collapse due to using the conducting Si substrate. Furthermore, attempts for normally off GaN-FETs were exam- ined. A hybrid metal-oxide-semiconductor HFET structure is a promising candidate for obtaining devices with a lower on-resistance ðRonÞ and a high breakdown voltage ðVbÞ.
448 citations