Proceedings ArticleDOI
Majority Logic: Prime Implicants and n-Input Majority Term Equivalence
Rajeswari Devadoss,Kolin Paul,Mahesh Balakrishnan +2 more
- pp 464-469
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TLDR
This work exploits the properties of Majority to create an efficient algorithm to generate the sums of all prime 1-implicants and all prime 0- Implicants of an n-input Majority term, both being canonical representations of Boolean functions.Abstract:
Recent advances in nanotechnology have led to the emergence of energy efficient circuit technologies like spintronics and domain wall magnets that use Majority gates as their primary logic elements. Logic synthesis that exploits these technologies demand an understanding of the mathematics of n-input Majority terms. One of the problems that turn up in such a study is the checking of equivalence of two n-input Majority terms on the same set of variables. We provide an algorithm based on prime implicants as a solution to this problem. In this quest, we extend the concept of implicants to two cases - 1-implicants and prime 1-implicants that imply a function evaluates to '1', and 0-implicants and prime 0-implicants that imply that it evaluates to '1'. We exploit the properties of Majority to create an efficient algorithm to generate the sums of all prime 1-implicants and all prime 0-implicants of an n-input Majority term, both being canonical representations of Boolean functions. As Majority and Threshold functions have been shown to be logically equivalent, our algorithms are applicable to Threshold functions as well. Also, being based on prime implicants, our algorithms improve on the known algorithm for equivalence checking for threshold logic terms.read more
Citations
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Equivalence Checking of Combinational Circuits using Boolean Expression Diagrams
TL;DR: In this paper, a data structure called Boolean expression diagrams (BEDs) and two algorithms for transforming a BED into a reduced ordered binary decision diagram (OBDD) are presented.
Journal ArticleDOI
A Novel Computing-in-Memory Platform Based on Hybrid Spintronic/CMOS Memory
TL;DR: A novel CiM platform based on hybrid spintronic/CMOS memory is proposed, which can work in memory mode and computing mode, and the performance of nonvolatile memory write operations is significantly improved and requirements for device fabrication are reduced by exploiting the toggle spin torques mechanism.
Journal ArticleDOI
Design of In-Memory Parallel-Prefix Adders
TL;DR: In this article, the authors proposed a parallel prefix adder to reduce the latency of in-memory adders by O(log(n)) in Resistive RAM (ReRAM).
Journal ArticleDOI
Equivalence Checking and Compaction of n-input Majority Terms Using Implicants of Majority
TL;DR: Being based on implicants of Majority, the algorithms improve on the known naive algorithms for equivalence checking and compaction for threshold logic terms and are applicable to Threshold functions as well.
References
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Journal ArticleDOI
A method of majority logic reduction for quantum cellular automata
TL;DR: A method for reducing the number of majority gates required for computing three-variable Boolean functions is developed to facilitate the conversion of sum-of-products expression into QCA majority logic.
Equivalence Checking of Combinational Circuits using Boolean Expression Diagrams
TL;DR: In this paper, a data structure called Boolean expression diagrams (BEDs) and two algorithms for transforming a BED into a reduced ordered binary decision diagram (OBDD) are presented.
Posted Content
Proposal For Neuromorphic Hardware Using Spin Devices
TL;DR: It is shown that the spin-based neuromorphic designs can achieve 15X-300X lower computation energy for these applications; as compared to state of art CMOS designs.
Proceedings ArticleDOI
Combinational equivalence checking for threshold logic circuits
TL;DR: This work addresses the problem of combinational equivalence checking for threshold circuits, and proposes a new algorithm, to obtain compact functional representation of threshold elements, using this polynomial time algorithm to develop a new methodology to verify threshold circuits.
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