MAPLE: multilevel adaptive placement for mixed-size designs
25 Mar 2012-pp 193-200
TL;DR: A new multilevel framework for large-scale placement called MAPLE is proposed that respects utilization constraints, handles movable macros and guides the transition between global and detailed placement.
Abstract: We propose a new multilevel framework for large-scale placement called MAPLE that respects utilization constraints, handles movable macros and guides the transition between global and detailed placement. In this framework, optimization is adaptive to current placement conditions through a new density metric. As a baseline, we leverage a recently developed at quadratic optimization that is comparable to prior multilevel frameworks in quality and runtime. A novel component called Progressive Local Refinement (ProLR) helps mitigate disruptions in wirelength that we observed in leading placers. Our placer MAPLE outperforms published empirical results --- RQL, SimPL, mPL6, NTUPlace3, FastPlace3, Kraftwerk and APlace3 -- across the ISPD 2005 and ISPD 2006 benchmarks, in terms of official metrics of the respective contests.
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TL;DR: This work presents a learning-based approach to chip placement, and shows that, in under 6 hours, this method can generate placements that are superhuman or comparable on modern accelerator netlists, whereas existing baselines require human experts in the loop and take several weeks.
Abstract: In this work, we present a learning-based approach to chip placement, one of the most complex and time-consuming stages of the chip design process. Unlike prior methods, our approach has the ability to learn from past experience and improve over time. In particular, as we train over a greater number of chip blocks, our method becomes better at rapidly generating optimized placements for previously unseen chip blocks. To achieve these results, we pose placement as a Reinforcement Learning (RL) problem and train an agent to place the nodes of a chip netlist onto a chip canvas. To enable our RL policy to generalize to unseen blocks, we ground representation learning in the supervised task of predicting placement quality. By designing a neural architecture that can accurately predict reward across a wide variety of netlists and their placements, we are able to generate rich feature embeddings of the input netlists. We then use this architecture as the encoder of our policy and value networks to enable transfer learning. Our objective is to minimize PPA (power, performance, and area), and we show that, in under 6 hours, our method can generate placements that are superhuman or comparable on modern accelerator netlists, whereas existing baselines require human experts in the loop and take several weeks.
139 citations
TL;DR: In this article, the authors presented a deep reinforcement learning approach to chip floorplanning, which can automatically generate chip floorplans that are superior or comparable to those produced by humans in all key metrics, including power consumption, performance and chip area.
Abstract: Chip floorplanning is the engineering task of designing the physical layout of a computer chip. Despite five decades of research1, chip floorplanning has defied automation, requiring months of intense effort by physical design engineers to produce manufacturable layouts. Here we present a deep reinforcement learning approach to chip floorplanning. In under six hours, our method automatically generates chip floorplans that are superior or comparable to those produced by humans in all key metrics, including power consumption, performance and chip area. To achieve this, we pose chip floorplanning as a reinforcement learning problem, and develop an edge-based graph convolutional neural network architecture capable of learning rich and transferable representations of the chip. As a result, our method utilizes past experience to become better and faster at solving new instances of the problem, allowing chip design to be performed by artificial agents with more experience than any human designer. Our method was used to design the next generation of Google’s artificial intelligence (AI) accelerators, and has the potential to save thousands of hours of human effort for each new generation. Finally, we believe that more powerful AI-designed hardware will fuel advances in AI, creating a symbiotic relationship between the two fields. Machine learning tools are used to greatly accelerate chip layout design, by posing chip floorplanning as a reinforcement learning problem and using neural networks to generate high-performance chip layouts.
124 citations
05 Nov 2012
TL;DR: The history of placement research, the progress leading up to the state of the art, and outstanding challenges are surveyed.
Abstract: Given the significance of placement in IC physical design, extensive research studies performed over the last 50 years addressed numerous aspects of global and detailed placement. The objectives and the constraints dominant in placement have been revised many times over, and continue to evolve. Additionally, the increasing scale of placement instances affects the algorithms of choice for high-performance tools. We survey the history of placement research, the progress achieved up to now, and outstanding challenges.
88 citations
Cites background or methods from "MAPLE: multilevel adaptive placemen..."
...0 [103], mFAR [66], Kraftwerk [145], FastPlace [158] and RQL [158], as well as SimPL [85,87], MAPLE [89] and ComPLx [88]....
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...Other placement-based approaches explicitly shift macros or cells during placement [31,89,157], or relegalize after every placement iteration [21, 45]....
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...0 [103], mFAR [66], Kraftwerk [145], FastPlace [158] and RQL [158], as well as SimPL [85,87], MAPLE [89] and ComPLx [88]....
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...[89] M.-C. Kim, N. Viswanathan, C. J. Alpert, I. L. Markov, S. Ramji, MAPLE: Multilevel Adaptive PLacEment for Mixed-size Designs , ISPD 2012, pp. 193-200....
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TL;DR: A novel GPU-accelerated placement framework DREAMPlace is proposed, by casting the analytical placement problem equivalently to training a neural network, to achieve speedup in global placement without quality degradation compared to the state-of-the-art multithreaded placer RePlAce.
Abstract: Placement for very large-scale integrated (VLSI) circuits is one of the most important steps for design closure We propose a novel GPU-accelerated placement framework DREAMPlace, by casting the analytical placement problem equivalently to training a neural network Implemented on top of a widely adopted deep learning toolkit PyTorch , with customized key kernels for wirelength and density computations, DREAMPlace can achieve around $40\times $ speedup in global placement without quality degradation compared to the state-of-the-art multithreaded placer RePlAce We believe this work shall open up new directions for revisiting classical EDA problems with advancements in AI hardware and software
87 citations
Cites background from "MAPLE: multilevel adaptive placemen..."
...Quadratic placement tackles the problem by iterating between an unconstrained wirelength minimization step and a rough legalization (LG) or spreading step [10]–[15]....
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...3003843 Analytical placement is the current state-of-the-art for VLSI placement [1]–[15]....
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TL;DR: A novel placement density function eDensity is developed, which models every object as positive charge and the density cost as the potential energy of the electrostatic system, which is more effective, generalized, simpler, and faster than previous works.
Abstract: We develop a flat, analytic, and nonlinear placement algorithm, ePlace, which is more effective, generalized, simpler, and faster than previous works. Based on the analogy between placement instance and electrostatic system, we develop a novel placement density function eDensity, which models every object as positive charge and the density cost as the potential energy of the electrostatic system. The electric potential and field distribution are coupled with density using a well-defined Poisson's equation, which is numerically solved by spectral methods based on fast Fourier transform (FFT). Instead of using the conjugate gradient (CG) nonlinear solver in previous placers, we propose to use Nesterov's method which achieves faster convergence. The efficiency bottleneck on line search is resolved by predicting the steplength using a closed-form equation of Lipschitz constant. The placement performance is validated through experiments on the ISPD 2005 and ISPD 2006 benchmark suites, where ePlace outperforms all state-of-the-art placers (Capo10.5, FastPlace3.0, RQL, MAPLE, ComPLx, BonnPlace, POLAR, APlace3, NTUPlace3, mPL6) with much shorter wirelength and shorter or comparable runtime. On average, of all the ISPD 2005 benchmarks, ePlace outperforms the leading placer BonnPlace with 2.83p shorter wirelength and runs 3.05× faster; and on average, of all the ISPD 2006 benchmarks, ePlace outperforms the leading placer MAPLE with 4.59p shorter wirelength and runs 2.84× faster.
68 citations
Cites background or methods or result from "MAPLE: multilevel adaptive placemen..."
...2007b], RQL [Viswanathan et al. 2007a], MAPLE [Kim et al. 2012], ComPLx (v13....
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...MAPLE: Multilevel adaptive placement for mixed-size designs....
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...0, RQL, MAPLE, ComPLx, BonnPlace, POLAR, APlace3, NTUPlace3, and mPL6, respectively. ePlace is faster than all the previous nonlinear placers....
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...0 [Viswanathan et al. 2007b], RQL [Viswanathan et al. 2007a], SimPL [Kim et al. 2010], MAPLE [Kim et al. 2012], ComPLx [Kim and Markov 2012], BonnPlace [Struzyna 2013], and POLAR [Lin et al. 2013]....
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...CP = Capo, FP = FastPlace, MPE = MAPLE, CPx = ComPLx, AP = APlace, NP = NTUPlace....
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References
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TL;DR: The authors present a placement method for cell-based layout styles that is composed of alternating and interacting global optimization and partitioning steps that are followed by an optimization of the area utilization.
Abstract: The authors present a placement method for cell-based layout styles. It is composed of alternating and interacting global optimization and partitioning steps that are followed by an optimization of the area utilization. Methods using the divide-and-conquer paradigm usually lose the global view by generating smaller and smaller subproblems. In contrast, GORDIAN maintains the simultaneous treatment of all cells over all global optimization steps, thereby considering constraints that reflect the current dissection of the circuit. The global optimizations are performed by solving quadratic programming problems that possess unique global minima. Improved partitioning schemes for the stepwise refinement of the placement are introduced. The area utilization is optimized by an exhaustive slicing procedure. The placement method is applied to real-world problems, and excellent results in terms of placement quality and computation time are obtained. >
567 citations
TL;DR: This work proposes a high-quality analytical placement algorithm considering wirelength, preplaced blocks, and density based on the log-sum-exp wirelength model proposed by Naylor and the multilevel framework and uses the conjugate gradient method to find better macro positions.
Abstract: In addition to wirelength, modern placers need to consider various constraints such as preplaced blocks and density. We propose a high-quality analytical placement algorithm considering wirelength, preplaced blocks, and density based on the log-sum-exp wirelength model proposed by Naylor and the multilevel framework. To handle preplaced blocks, we use a two-stage smoothing technique, i.e., Gaussian smoothing followed by level smoothing, to facilitate block spreading during global placement (GP). The density is controlled by white-space reallocation using partitioning and cut-line shifting during GP and cell sliding during detailed placement. We further use the conjugate gradient method with dynamic step-size control to speed up the GP and macro shifting to find better macro positions. Experimental results show that our placer obtains very high-quality results.
260 citations
01 Jun 1991
TL;DR: This paper addresses the problem of cell placement by joining the linear objective with an efficient quadratic programming approach, and by applying a refined iterative partitioning scheme, and obtains placements of excellent quality.
Abstract: This paper addresses the problem of cell placement which is considered crucial for layout quality. Based on the combined analytical and partitioning strategy successfully applied in the GORDIAN placement tool, we discuss the consequences of using linear or quadratic objective functions. By joining the linear objective with an efficient quadratic programming approach, and by applying a refined iterative partitioning scheme, we obtain placements of excellent quality. The effect of a quadratic and a linear objective function on the chip area after final routing is demonstrated for benchmark circuits and other circuits with up to 21 000 cells.
239 citations
03 Apr 2005
TL;DR: A generalized force-directed algorithm embedded in mPL2's multilevel framework is presented, which produces the shortest wirelength among all published placers with very competitive runtime on the IBM circuits used in [29].
Abstract: Automatic circuit placement has received renewed interest recently given the rapid increase of circuit complexity, increase of interconnect delay, and potential sub-optimality of existing placement algorithms [13]. In this paper we present a generalized force-directed algorithm embedded in mPL2's [12] multilevel framework. Our new algorithm, named mPL5, produces the shortest wirelength among all published placers with very competitive runtime on the IBM circuits used in [29]. The new contributions and enhancements are: (1) We develop a new analytical placement algorithm using a density constrained minimization formulation which can be viewed as a generalization of the force-directed method in [16]; (2) We analyze and identify the advantages of our new algorithm over the force-directed method; (3) We successfully incorporate the generalized force-directed algorithm into a multilevel framework which significantly improves wirelength and speed. Compared to Capo9.0, our algorithm mPL5 produces 8% shorter wirelength and is 2X faster. Compared to Dragon3.01, mPL5 has 3% shorter wirelength and is 12X faster. Compared to Fengshui5.0, it has 5% shorter wirelength and is 2X faster. Compared to the ultra-fast placement algorithm: FastPlace, mPL5 produces 8% shorter wirelength but is 6X slower. A fast mode of mPL5 (mPL5-fast) can produce 1% shorter wirelength than Fast-Place1.0 and is only 2X slower. Moreover, mPL5-fast has demonstrated better scalability than FastPlace1.0.
200 citations
09 Apr 2006
TL;DR: The multilevel placement package mPL6 combines improved implementations of the global placer mPL5 and the XDP legalizer and detailed placer and the ASPDAC06 and consistently produces robust, high-quality solutions to difficult instances of mixed-size placement in fast and scalable run time.
Abstract: The multilevel placement package mPL6 combines improved implementations of the global placer mPL5 (ISPD05) and the XDP legalizer and detailed placer (ASPDAC06). It consistently produces robust, high-quality solutions to difficult instances of mixed-size placement in fast and scalable run time. Best-choice clustering (ISPD05) is used to construct a hierarchy of problem formulations. Generalized force-directed placement guides global placement at each level of the cluster hierarchy. During the declustering pass from coarsest to finest level, large movable objects are gradually fixed in positions without overlapping with one another. This progressive legalization of large objects during continuous optimization supports determination of a completely overlap-free configuration as close as possible to the continuous solution. Various discrete heuristics are applied to this legalized placement in order to improve the final wirelength.
199 citations