Mapping Time-Critical Safety-Critical Cyber Physical Systems to Hybrid FPGAs
25 Aug 2014-pp 31-36
TL;DR: Hybrid FPGAs, combining a processor and reconfigurable fabric on a single die, allow for parallel hardware implementation of complex sensor processing tightly coupled with the flexibility of software on a processor, enabling ECU consolidation and bandwidth reduction.
Abstract: Cyber Physical Systems (CPSs), such as those found in modern vehicles, include a number of important time and safety-critical functions. Traditionally, applications are mapped to several dedicated electronic control units (ECUs), and hence, as new functions are added, compute weight and cost increase considerably.%ECU consolidation, where multiple functions are combined on fewer ECUs is an important area, but traditional software ECUs fail to offer the required performance, parallelism, and isolation to support this. With increasing computational and communication demands, traditional software ECUs fail to offer the required performance to provide determinism and predictability, while multi-core approaches fail to provide sufficient isolation between tasks. Hybrid FPGAs, combining a processor and reconfigurable fabric on a single die, allow for parallel hardware implementation of complex sensor processing tightly coupled with the flexibility of software on a processor. We demonstrate the advantages of such architectures in consolidating distributed processing with predictability, determinism and isolation, enabling ECU consolidation and bandwidth reduction.
Citations
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TL;DR: VEGa is presented, a configurable vehicular Ethernet gateway architecture utilising a hybrid FPGA to closely couple software control on a processor with dedicated switching circuit on the reconfigurable fabric, which enables the switching behaviour to be altered at run-time under software control.
Abstract: Modern vehicles employ a large amount of distributed computation and require the underlying communication scheme to provide high bandwidth and low latency. Existing communication protocols like Controller Area Network (CAN) and FlexRay do not provide the required bandwidth, paving the way for adoption of Ethernet as the next generation network backbone for in-vehicle systems. Ethernet would co-exist with safety-critical communication on legacy networks, providing a scalable platform for evolving vehicular systems. This requires a high-performance network gateway that can simultaneously handle high bandwidth, low latency, and isolation; features that are not achievable with traditional processor based gateway implementations. We present VEGa, a configurable vehicular Ethernet gateway architecture utilising a hybrid FPGA to closely couple software control on a processor with dedicated switching circuit on the reconfigurable fabric. The fabric implements isolated interface ports and an accelerated routing mechanism, which can be controlled and monitored from software. Further, reconfigurability enables the switching behaviour to be altered at run-time under software control, while the configurable architecture allows easy adaptation to different vehicular architectures using high-level parameter settings. We demonstrate the architecture on the Xilinx Zynq platform and evaluate the bandwidth, latency, and isolation using extensive tests in hardware.
28 citations
Cites background or methods from "Mapping Time-Critical Safety-Critic..."
...however, they do not offer sufficient computational capability to implement complex algorithms with time-bound performance [8]....
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...The hybrid architecture enables scalable and parallel implementations of complex processing blocks in the PL, while retaining software-based control through the tightly coupled ARM cores [8]....
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15 Jun 2015
TL;DR: CoPR is presented, a fully automated framework for implementing PR based adaptive hardware systems on the Zynq family of hybrid FPGAs, and a case-study on the design of a multi-standard adaptive radio system.
Abstract: Dynamically adaptive systems respond to environmental conditions by modifying their processing at runtime, selecting alternative configurations of computation. While FPGAs with partial reconfiguration (PR) seem to offer an ideal platform for flexible hardware, designing such systems is difficult, and no standardised model and methodology exists. We present CoPR, a fully automated framework for implementing PR based adaptive hardware systems on the Zynq family of hybrid FPGAs. The designer specifies a set of valid configurations comprising hardware modules. CoPR automates partitioning of modules into regions, floorplanning on the FPGA fabric, and generation of partial bitstreams. The runtime framework offers an abstracted view of system configuration through an API that allows the designer to focus on adaptation software without considering details of the underlying hardware. We present a case-study on the design of a multi-standard adaptive radio system.
26 citations
01 Jan 2015
TL;DR: This paper presents a taxonomy of fault tolerance techniques to tolerate permanent faults, as well as map it to real-time mixed-criticality requirements based on the extend of fault coverage that in turn influences the associated assurance.
Abstract: Adopting mixed-criticality architectures enable safe sharing of computational resources between tasks of different criticalities consequently leading to reduced Size, Weight and Power (SWaP) requirements. A majority of the research in mixed-criticality systems focuses on scheduling tasks whose Worst Case Execution Times (WCETs) are certified to varying levels of assurances. If any given task overruns its WCET, the system switches to a higher criticality and all the lower criticality tasks are discarded to make time for the execution of higher criticality tasks. Task execution time overruns are transient faults that are typically tolerated by simply executing an alternate task before the original deadline, or, by discarding the failed task to prevent it from interfering with higher criticality tasks. However, permanent faults such as processor failures can render the system to be useless, many times leading to unsafe states. In this paper we present a taxonomy of fault tolerance techniques to tolerate permanent faults, as well as map it to real-time mixed-criticality requirements based on the extend of fault coverage that in turn influences the associated assurance.
11 citations
Cites background from "Mapping Time-Critical Safety-Critic..."
...Assurance Mechanism: The highest criticality tasks may be implemented on dedicated hardware to ensure isolation (as is typically done in many systems [14]), and a high integrity voter implemented as a simple electronic circuit performs voting....
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TL;DR: In this article, a robot-based intelligent management design that can intelligently manage the opening growth environments of crops is proposed, where a binarized neural network (BNN) hardware module provides the real-time and accurate detection of target crops, while cryptographic hardware functions ensure the security of sensor data transfers in an unsupervised environment.
9 citations
11 May 2016
7 citations
Cites methods from "Mapping Time-Critical Safety-Critic..."
...The hybrid architecure enables scalable and parallel implementations of complex processing blocks in the PL, while retaining software-based control through the tightly coupled ARM cores [187]....
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References
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TL;DR: This paper explains the initiatives for automation in different levels of transportation system with a specific emphasis on the vehicle-level automation, and the impact of automation/warning systems on each of the above-mentioned factors.
Abstract: This paper looks into recent developments and research trends in collision avoidance/warning systems and automation of vehicle longitudinal/lateral control tasks. It is an attempt to provide a bigger picture of the very diverse, detailed and highly multidisciplinary research in this area. Based on diversely selected research, this paper explains the initiatives for automation in different levels of transportation system with a specific emphasis on the vehicle-level automation. Human factor studies and legal issues are analyzed as well as control algorithms. Drivers' comfort and well being, increased safety, and increased highway capacity are among the most important initiatives counted for automation. However, sometimes these are contradictory requirements. Relying on an analytical survey of the published research, we will try to provide a more clear understanding of the impact of automation/warning systems on each of the above-mentioned factors. The discussion of sensory issues requires a dedicated paper due to its broad range and is not addressed in this paper.
823 citations
"Mapping Time-Critical Safety-Critic..." refers background in this paper
...Modern vehicles, on the other hand, contain so many systems, that 20-100 million lines of code run on 50-100 ECUs to provide all the necessary control and comfort features [10]....
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BMW1
TL;DR: In this article, the authors describe the BMW Active Cruise Control (ACC) system which adds a headway control function to the speed control function of conventional cruise control systems, including the system capabilities, limits, function design and system philosophy.
Abstract: This paper describes the BMW Active Cruise Control (ACC) system which adds a headway control function to the speed control function of conventional cruise control systems. The functions of the ACC are described, including the system capabilities, limits, function design and system philosophy. This is followed by a description of the system, its components, and its control functions. The paper concludes with a discussion regarding the safety concepts of the combined sensor control unit and of the entire system network.
81 citations
"Mapping Time-Critical Safety-Critic..." refers background in this paper
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TL;DR: This paper proposes the use of programmable hardware to accelerate the calculation of GLCM and Haralick texture features and as an example of the speedup offered by programmable logic, a multispectral computer vision system for automatic diagnosis of prostatic cancer has been implemented.
Abstract: Grey Level Co-occurrence Matrix (GLCM), one of the best known tool for texture analysis, estimates image properties related to second-order statistics. These image properties commonly known as Haralick texture features can be used for image classification, image segmentation, and remote sensing applications. However, their computations are highly intensive especially for very large images such as medical ones. Therefore, methods to accelerate their computations are highly desired. This paper proposes the use of programmable hardware to accelerate the calculation of GLCM and Haralick texture features. Further, as an example of the speedup offered by programmable logic, a multispectral computer vision system for automatic diagnosis of prostatic cancer has been implemented. The performance is then compared against a microprocessor based solution.
75 citations
"Mapping Time-Critical Safety-Critic..." refers background in this paper
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16 Apr 2007
TL;DR: A reconfigurable hardware architecture for the acceleration of video-based driver assistance applications in future automotive systems that makes use of the partial dynamic reconfiguration capabilities of Xilinx Virtex FPGAs.
Abstract: In this paper we show a reconfigurable hardware architecture for the acceleration of video-based driver assistance applications in future automotive systems. The concept is based on a separation of pixel-level operations and high level application code. Pixel-level operations are accelerated by coprocessors, whereas high level application code is implemented fully programmable on standard PowerPC CPU cores to allow flexibility for new algorithms. In addition, the application code is able to dynamically reconfigure the coprocessors available on the system, allowing for a much larger set of hardware accelerated functionality than would normally fit onto a device. This process makes use of the partial dynamic reconfiguration capabilities of Xilinx Virtex FPGAs.
71 citations
TL;DR: This letter presents some initial research on the place of reconfigurable computing in future vehicles, providing both static and dynamic flexibility, with high computational capabilities, at lower power consumption.
Abstract: Modern vehicles incorporate a significant amount of computation, which has led to an increase in the number of computational nodes and the need for faster in-vehicle networks Functions range from noncritical control of electric windows, through critical drive-by-wire systems, to entertainment applications; as more systems are automated, this variety and number will continue to increase Accommodating the varying computational and communication requirements of such a diverse range of functions requires flexible networks and embedded computing devices As the number of electronic control units (ECUs) increases, power and efficiency become more important, more so in next-generation electric vehicles Moreover, predictability and isolation of safety-critical functions are nontrivial challenges when aggregating multiple functions onto fewer nodes Reconfigurable computing can play a key role in addressing these challenges, providing both static and dynamic flexibility, with high computational capabilities, at lower power consumption Reconfigurable hardware also provides resources and methods to address deterministic requirements, reliability and isolation of aggregated functions This letter presents some initial research on the place of reconfigurable computing in future vehicles
57 citations
"Mapping Time-Critical Safety-Critic..." refers background in this paper
...In [18], the authors discuss the application of FPGA partial reconfiguration to redundancy in vehicular networks....
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