Matching properties of MOS transistors
TL;DR: In this paper, the matching properties of the threshold voltage, substrate factor, and current factor of MOS transistors have been analyzed and measured, and the matching results have been verified by measurements and calculations on several basic circuits.
Abstract: The matching properties of the threshold voltage, substrate factor, and current factor of MOS transistors have been analyzed and measured. Improvements to the existing theory are given, as well as extensions for long-distance matching and rotation of devices. Matching parameters of several processes are compared. The matching results have been verified by measurements and calculations on several basic circuits. >
Citations
More filters
University of Zurich1, Spanish National Research Council2, University of New South Wales3, University of Sydney4, Johns Hopkins University5, University of Manchester6, University of Oslo7, Centre national de la recherche scientifique8, Heidelberg University9, University of California, San Diego10, Stanford University11, Howard Hughes Medical Institute12
TL;DR: The most common building blocks and techniques used to implement these circuits, and an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance-based Hodgkin–Huxley models to bi-dimensional generalized adaptive integrate and fire models.
Abstract: Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain-machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this paper we describe the most common building blocks and techniques used to implement these circuits, and present an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance-based Hodgkin-Huxley models to bi-dimensional generalized adaptive integrate and fire models. We compare the different design methodologies used for each silicon neuron design described, and demonstrate their features with experimental results, measured from a wide range of fabricated VLSI chips.
1,559 citations
Cites background from "Matching properties of MOS transist..."
...However, in the weak-inversion domain mismatch effects are more pronounced than in the strong-inversion regime (Pelgrom et al., 1989), and often require learning, adaptation or other compensation schemes....
[...]
01 Aug 1991-Nuclear Instruments & Methods in Physics Research Section A-accelerators Spectrometers Detectors and Associated Equipment
TL;DR: In this article, the matching properties of the threshold voltage, substrate factor and current factor of MOS transistors have been analyzed and measured, and the matching results have been verified by measurements and calculations on a band-gap reference circuit.
Abstract: The matching properties of the threshold voltage, substrate factor and current factor of MOS transistors have been analysed and measured. Improvements of the existing theory are given, as well as extensions for long distance matching and rotation of devices. The matching results have been verified by measurements and calculations on a band-gap reference circuit.
1,158 citations
CERN1
21 Oct 2007-Nuclear Instruments & Methods in Physics Research Section A-accelerators Spectrometers Detectors and Associated Equipment
TL;DR: In this paper, the authors proposed a novel approach for the readout of a TPC at the future linear collider is to use a CMOS pixel detector combined with some kind of gas gain grid.
Abstract: A novel approach for the readout of a TPC at the future linear collider is to use a CMOS pixel detector combined with some kind of gas gain grid. A first test using the photon counting chip Medipix2 with GEM or Micromegas demonstrated the feasibility of such an approach. Although this experiment demonstrated that single primary electrons could be detected the chip did not provide information on the arrival time of the electron in the sensitive gas volume nor did it give any indication of the quantity of charge detected. The Timepix chip uses an external clock with a frequency of up to 100 MHz as a time reference. Each pixel contains a preamplifier, a discriminator with hysteresis and 4-bit DAC for threshold adjustment, synchronization logic and a 14-bit counter with overflow control. Moreover, each pixel can be independently configured in one of four different modes: masked mode: pixel is off, counting mode: 1-count for each signal over threshold, TOT mode: the counter is incremented continuously as long as the signal is above threshold, and arrival time mode: the counter is incremented continuously from the time the first hit arrives until the end of the shutter. The chip resembles very much the Medipix2 chip physically and can be readout using slightly modified versions of the various existing systems. This paper presents the main features of the new design, electrical measurements and some first images.
1,004 citations
TL;DR: Test results show that even higher resolutions can be achieved using the VDL method, and resolutions down to 5 ps are demonstrated to be obtainable.
Abstract: This paper describes a CMOS time-to-digital converter (TDC) integrated circuit utilizing tapped delay lines. A technique that allows the achievement of high resolution with low dead-time is presented, The technique is based on a Vernier delay line (VDL) used in conjunction with an asynchronous read-out circuitry. A delay-locked loop (DLL) is used to stabilize the resolution against process variations and ambient conditions. A test circuit fabricated in a standard 0.7-/spl mu/m digital CMOS process is presented. The TDC contains 128 delay stages and achieves 30-ps resolution, stabilized by the DLL, with the accuracy exceeding /spl plusmn/1 LSB. Test results show that even higher resolutions can be achieved using the VDL method, and resolutions down to 5 ps are demonstrated to be obtainable.
724 citations
TL;DR: Mixed hardware–software neural-network implementations that involve up to 204,900 synapses and that combine long-term storage in phase-change memory, near-linear updates of volatile capacitors and weight-data transfer with ‘polarity inversion’ to cancel out inherent device-to-device variations are demonstrated.
Abstract: Neural-network training can be slow and energy intensive, owing to the need to transfer the weight data for the network between conventional digital memory chips and processor chips. Analogue non-volatile memory can accelerate the neural-network training algorithm known as backpropagation by performing parallelized multiply-accumulate operations in the analogue domain at the location of the weight data. However, the classification accuracies of such in situ training using non-volatile-memory hardware have generally been less than those of software-based training, owing to insufficient dynamic range and excessive weight-update asymmetry. Here we demonstrate mixed hardware-software neural-network implementations that involve up to 204,900 synapses and that combine long-term storage in phase-change memory, near-linear updates of volatile capacitors and weight-data transfer with 'polarity inversion' to cancel out inherent device-to-device variations. We achieve generalization accuracies (on previously unseen data) equivalent to those of software-based training on various commonly used machine-learning test datasets (MNIST, MNIST-backrand, CIFAR-10 and CIFAR-100). The computational energy efficiency of 28,065 billion operations per second per watt and throughput per area of 3.6 trillion operations per second per square millimetre that we calculate for our implementation exceed those of today's graphical processing units by two orders of magnitude. This work provides a path towards hardware accelerators that are both fast and energy efficient, particularly on fully connected neural-network layers.
693 citations
References
More filters
TL;DR: In this paper, a characterization methodology is presented that accurately predicts the mismatch in drain current over a wide operating range using a minimum set of measured data and the physical causes of mismatch are discussed in detail for both p- and n-channel devices.
Abstract: A characterization methodology is presented that accurately predicts the mismatch in drain current over a wide operating range using a minimum set of measured data. The physical causes of mismatch are discussed in detail for both p- and n-channel devices. Statistical methods are used to develop analytical models that relate the mismatch to the device dimensions. It is shown that these models are valid for small-geometry devices only. Extensive experimental data from a 3-/spl mu/m CMOS process are used to verify the models. The application of the transistor matching studies to the design of a high-performance digital-to-analog converter (DAC) is discussed. A circuit design methodology is presented that highlights the close interaction between the circuit yield and the matching accuracy of devices. It has been possible to achieve a circuit yield of greater than 97% as a result of the knowledge generated regarding the matching behavior of transistors and due to the systematic design approach.
707 citations
TL;DR: Results indicate that a 9-bit matching accuracy can be obtained for capacitors and an 8-bit accuracy for MOS current sources without difficulty if the systematic error sources are reduced using proper design and layout techniques.
Abstract: Explicit formulas are derived using statistical methods for the random errors affecting capacitance and current ratios in MOS integrated circuits. They give the dependence of each error source on the physical dimensions, the standard deviations of the fabrication parameters, the bias conditions, etc. Experimental results, obtained for both matched capacitors and matched current sources using a 3.5-/spl mu/m NMOS technology, confirmed the theoretical predictions. Random effects represent the ultimate limitation on the achievable accuracy of switched-capacitor filters, D/A converters, and other MOS analog integrated circuits. The results indicate that a 9-bit matching accuracy can be obtained for capacitors and an 8-bit accuracy for MOS current sources without difficulty if the systematic error sources are reduced using proper design and layout techniques.
339 citations
Book•
01 Nov 1983
TL;DR: In this paper, the authors present a framework for robustness, breakdown point, and influence function for probability distributions. But they do not consider the effect of variance on robustness.
Abstract: 1. Introduction and Summary.- 1.1. History and main contributions.- 1.2. Why robust estimations?.- 1.3. Summary.- A The Theoretical Background.- 2. Sample spaces, distributions, estimators.- 2.1. Introduction.- 2.2. Example.- 2.3. Metrics for probability distributions.- 2.4. Estimators seen as functionals of distributions.- 3. Robustness, breakdown point and influence function.- 3.1. Definition of robustness.- 3.2. Definition of breakdown point.- 3.3. The influence function.- 4. The jackknife method.- 4.1. Introduction.- 4.2. The jackknife advanced theory.- 4.3. Case study.- 4.4. Comments.- 5. Bootstrap methods, sampling distributions.- 5.1. Bootstrap methods.- 5.2. Sampling distribution of estimators.- B.- 6. Type M estimators.- 6.1. Definition.- 6.2. Influence function and variance.- 6.3. Robust M estimators.- 6.4. Robustness, quasi-robustness and non-robustness.- 6.4.1. Statement of the location problem.- 6.4.2. Least powers.- 6.4.3. Huber's function.- 6.4.4. Modification to Huber's proposal.- 6.4.5. Function "Fair".- 6.4.6. Cauchy-s function.- 6.4.7. Welsch-s function.- 6.4.8. "Bisquare" function.- 6.4.9. Andrews's function.- 6.4.10. Selection of the ?-function.- 7. Type L estimators.- 7.1. Definition.- 7.2. Influence function and variance.- 7.3. The median and related estimators.- 8. Type R estimator.- 8.1. Definition.- 8.2. Influence function and variance.- 9. Type MM estimators.- 9.1. Definition.- 9.2. Influence function and variance.- 9.3. Linear model and robustness - Generalities.- 9.4. Scale of residuals.- 9.5. Robust linear regression.- 9.6. Robust estimation of multivariate location and scatter.- 9.7. Robust non-linear regression.- 9.8. Numerical methods.- 9.8.1. Relaxation methods.- 9.8.2. Simultaneous solutions.- 9.8.3 Solution of fixed-point and non-linear equations.- 10. Quantile estimators and confidence intervals.- 10.1. Quantile estimators.- 10.2. Confidence intervals.- 11. Miscellaneous.- 11.1. Outliers and their treatment.- 11.2. Analysis of variance, constraints on minimization.- 11.3. Adaptive estimators.- 11.4. Recursive estimators.- 11.5. Concluding remark.- 12. References.- 13. Subject index.
262 citations
TL;DR: In this paper, the effects of random edge variations and deviations of oxide thickness and permittivity are examined, and it is shown that edge effects introduce a relative capacitance error /spl Delta C/C/spl alpha C/SUP -3/4/, while the oxide variations cause /spl C/c/spl α C/ SUP -1/2/.
Abstract: The effects of random edge variations and deviations of oxide thickness and permittivity are examined. Making only a few basic assumptions, it is shown that edge effects introduce a relative capacitance error /spl Delta/C/C/spl alpha/C/SUP -3/4/, while the oxide variations cause /spl Delta/C/C/spl alpha/C/SUP -1/2/. Error bounds are derived for C in terms of the variances of the linear dimensions and oxide permittivity. For a capacitor C realized as a parallel connection of n unit capacitors of values C/n, the relative error caused by edge effects is n/SUP 1/4/ times larger than for a single capacitor of value C. The relative error due to oxide variations remains the same for the two realizations. All theoretical results agree with physical consideration, as well as the Monte Carlo simulations performed.
153 citations
TL;DR: Standard process CMOS/SOS technology has been applied in the design of a 6 bit parallel 20 MHz A/D converter that may be interconnected in series to obtain 7 bit resolution or in parallel to obtain nearly 40 MHz data rates.
Abstract: Standard process CMOS/SOS technology has been applied in the design of a 6 bit parallel 20 MHz A/D converter. Two chips may be interconnected in a series to obtain 7 bit resolution or in parallel to obtain nearly 40 MHz data rates. Design factors and accuracy requirements are reviewed.
121 citations