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Proceedings ArticleDOI

Measurement of Local Residual Stress of a Flip Chip Structure Using a Stress Sensing Chip

01 Jan 2005-pp 1135-1140
TL;DR: In this article, local residual stress at a surface of a silicon chip mounted on a substrate using flip chip technology was measured using a stress sensor chip that was composed of 168 strain gauges of 10-μm in length.
Abstract: Local residual stress at a surface of a silicon chip mounted on a substrate using flip chip technology was measured using a stress sensor chip that was composed of 168 strain gauges of 10-μm in length. Each strain gauge was made of polycrystalline silicon films deposited on a silicon wafer. The periodic stress distribution was measured at a surface of the sensor chip between two bumps. Five gauges were aligned at a interval of 20-μm between the bumps. When the thickness of the chip was less than 200 μm, the amplitude of the stress increased drastically, as was predicted by a finite element analysis. The amplitude of the stress reached about 150 MPa, when the thickness of the chip was thinned to 50 μm. The amplitude of the stress is a strong function of the thickness of a silicon chip and the intervals of the bumps.Copyright © 2005 by ASME
Citations
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Journal ArticleDOI
Kohta Nakahira1, Hironori Tago1, Fumiaki Endo1, Ken Suzuki1, Hideo Miura1 
TL;DR: In this article, the dominant structural factors of the local residual stress in a silicon chip are investigated quantitatively based on the results of a three-dimensional finite element analysis and the measurement of a chip using stress sensor chips.
Abstract: Since the thickness of stacked silicon chips in 3D integration has been thinned to less than 100 μm, the local thermal deformation of the chips has increased drastically because of the decrease of the flexural rigidity of the thinned chips. The clear periodic thermal deformation and thus, the local distribution of thermal residual stress appears in the stacked chips due to the periodic alignment of metallic bumps, and they sometimes deteriorate mechanical and electrical reliability of electronic products. In this paper, the dominant structural factors of the local residual stress in a silicon chip are investigated quantitatively based on the results of a three-dimensional finite element analysis and the measurement of the local residual stress in a chip using stress sensor chips. The piezoresistive strain gauges were embedded in the sensor chips. The length of each gauge was 2 μm, and an unit cell consisted of four gauges with different crystallographic directions. This alignment of the strain gauges enables us to measure the tensor component of three-dimensional stress fields separately. Test flip chip substrates were made of silicon chip on which the area-arrayed tin/copper bumps were electroplated. The width of a bump was fixed at 200 μm, and the bump pitch was varied from 400 μm to 1000 μm. The thickness of the copper bump was about 40 μm and that of tin layer was about 10 μm. This tin layer was used for the formation of rigid joint by alloying it with copper interconnection formed on a stress sensing chip. The measured amplitude of the residual stress increased from about 30 MPa to 250 MPa depending on the combination of materials such as bump, underfill, and interconnections. It was confirmed that both the material constant of underfill and the alignment structure of fine bumps are the dominant factors of the local deformation and stress of a silicon chip mounted on area-arrayed metallic bumps. It was also confirmed that not only the control of mechanical properties of electroplated copper thin films, but also the hound’s-tooth alignment of a through silicon via and a bump are indispensable for minimizing the packaging-induced stress in the three-dimensionally mounted chips. This test chip is very effective for evaluating the packaging-process-induced stress in 3D stacked chips quantitatively.

8 citations

Journal ArticleDOI
TL;DR: In this paper, Shin-Saito et al. reported that 2.2 μm of the 2.5 μm was spent on a 2.4 μm-sized container.
Abstract: フリップチップ実装構造内では構造材料であるシリコンや金属バンプ,アンダーフィル,樹脂基板などの弾性率および線膨張係数の相違に起因して局所残留応力分布が発生する。この残留応力の変動振幅が局所的に最大で300 MPaにも達することを,三次元応力解析と試作したゲージ長2 μmのピエゾ抵抗ゲージを搭載したセンサチップを用いて明らかにした。また,Siチップ面内の直交二軸方向の垂直応力の値が変形拘束物となる金属バンプからの距離に依存して大きく変化し,チップ面内のバンプ配置位置に依存して二軸等方的な場が形成される場所と最大で150 MPa以上の差が発生する異方的な場が形成される場所が混在することも明らかにした。

4 citations

Proceedings ArticleDOI
01 Nov 2007
TL;DR: In this article, the authors proposed the optimum stacked structures for minimizing the residual stress based on a finite element analysis when the thickness of the upper and bottom chips are thinned from 100 mum to 30 mum, regardless of the material of a substrate.
Abstract: Since mechanical stress sometimes degrades both electronic functions and reliability of LSI chips, it is very important to control the residual stress in them to assure their highly reliable performance The authors have already found that the local residual stress distribution on the transistor formation surface of LSIs changes significantly depending on their assembly structure In addition, we have found that the dominant structural factors that determine the distribution are the thickness of a chip, thermal expansion coefficient of underfill material and the shape and the relative position of bumps among stacked chips In this study, we proposed the optimum stacked structures for minimizing the residual stress based on a finite element analysis When the thickness of the upper and bottom chips are thinned from 100 mum to 30 mum, the average value of the normal stress increased monotonically regardless of the material of a substrate The rate of the increase of the average value was about 06 MPa/mum when the material of the substrate was silicon, while the rate of the increase was about 20 MPa/mum when the substrate was an organic one On the other hand, the maximum amplitude of the normal stress in the both chips mounted on an organic substrate was decreased to about 0 MPa, while the maximum amplitude of the normal stress in the stacked chips mounted on a Si substrate changed complicatedly Therefore, it can be said that a Si substrate is effective for minimizing the increase of the average vale of the normal stress, while an organic substrate is effective for minimizing the maximum amplitude of the normal stress by thinning of the chip But, it was also found that there was no way to decrease both the average stress and the maximum amplitude of the residual stress at the same time It is very important, therefore, to optimize the structure of each product by considering the most important part of the stress that dominates the electronic performance of the product However, it should be also noted that the thermal residual stress in the whole structure can not be made 0 because there is the difference of material properties among LSI chips, bumps, underfill and substrates Thus, the stress sensitivity of electronic performance and reliability of each chip should be evaluated before this structural design

4 citations


Cites background from "Measurement of Local Residual Stres..."

  • ...factors that determine the distribution are the thickness of a chip, thermal expansion coefficient of underfill material and the shape of bumps [5]....

    [...]

Proceedings ArticleDOI
Kohta Nakahira1, Hironori Tago1, Fumiaki Endo1, Ken Suzuki1, Hideo Miura1 
01 Jan 2011
TL;DR: In this article, the dominant structural factors of the local residual stress in a silicon chip are discussed quantitatively based on the results of a three-dimensional finite element analysis and the measurement of a chip using stress sensor chips.
Abstract: Since the thickness of the stacked silicon chips in 3D integration has been thinned to less than 100 μm, the local thermal deformation of the chips has increased drastically because of the decrease of the flexural rigidity of the thinned chips. The clear periodic thermal deformation and thus, the thermal residual stress distribution appears in the stacked chips due to the periodic alignment of metallic bumps, and they deteriorate the reliability of products. In this paper, the dominant structural factors of the local residual stress in a silicon chip are discussed quantitatively based on the results of a three-dimensional finite element analysis and the measurement of the local residual stress in a chip using stress sensor chips. The piezoresistive strain gauges were embedded in the sensor chips. The length of each gauge was 2 μm, and an unit cell consisted of 4 gauges with different crystallographic directions. This alignment of strain gauges enables to measure the tensor component of three-dimensional stress fields separately. Test flip chip substrates were made by silicon chip on which the area-arrayed tin/copper bumps were electroplated. The width of a bump was fixed at 200 μm, and the bump pitch was varied from 400 μm to 1000 μm. The thickness of the copper layer was about 40 μm and that of tin layer was about 10 μm. This tin layer was used for the rigid joint formation by alloying with copper interconnection formed on a stress sensing chip. The measured amplitude of the residual stress increased from about 30 MPa to 250 MPa depending on the combination of materials such as bump, underfill, and interconnections. It was confirmed that both the material constant of underfill and the alignment structure of fine bumps are the dominant factors of the local deformation and stress of a silicon chip mounted on area-arrayed metallic bumps. It was also confirmed experimentally that both the hound’s-tooth alignment between a TSV (Through Silicon Via) and a bump and control of mechanical properties of electroplated copper thin films used for the TSV and bump is indispensable in order to minimize the packaging-induced stress in the three-dimensionally mounted chips. This test chip is very effective for evaluating the packaging-process induced stress in 3D stacked chips quantitatively.© 2011 ASME

3 citations

Proceedings ArticleDOI
01 Oct 2006
TL;DR: In this article, the authors discussed the reliability issues such as cracking of LSI chips and shift or deterioration of electronic performance of them caused by mechanical stress and strain in multi-device subassembly (MDS) structures.
Abstract: Mechanical reliability issues such as cracking of LSI chips and shift or deterioration of electronic performance of them caused by mechanical stress and strain in multi devices sub-assembly (MDS) structures were discussed analytically and experimentally Local thermal deformation due to thinning of the LSI chips for mobile application causes large distribution of residual stress from ?300 MPa to +150 MPa in the chips The values of the maximum and the minimum stresses are strong functions of the thickness of the LSI chips and period of area-arrayed small bumps In flip chip assembly structures, periodic stress or strain distribution appears in the thinned chips depending on the period of the area-arrayed bumps The amplitude of the stress often exceeds 100 MPa, and it may cause the change of electronic performance and reliability of devices In addition, both the amplitude and the average stress vary among the three-dimensionally stacked thin chips due to macroscopic bending of the assembled structure Therefore, it is very important to optimize the MDS structures to minimize the stress and thus, to improve the reliability of products

2 citations


Cites background or result from "Measurement of Local Residual Stres..."

  • ...This value agrees well with the result of a single chip assembly with the same bump alignment [6][7]....

    [...]

  • ...a polycrystalline silicon thin films by applying the piezoresistive effect of silicon [6]-[7]....

    [...]