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Proceedings ArticleDOI

Measuring Area-Complexity Using Boolean Difference

05 Jan 2013-pp 245-250
TL;DR: This paper demonstrates how to capture the area-complexity of a Boolean function using the complexity of its Boolean derivatives using the theory of Boolean difference and Taylor expansion for Boolean functions.
Abstract: For a combinational circuit, area-complexity is a measure that estimates the logic area of the circuit without mapping to logic gates. Several measures like literal count, number of primary input/outputs, etc. have been used in the past as area-complexity metrics. In this paper, we propose a novel area-complexity measure using the theory of Boolean difference and Taylor expansion for Boolean functions. We demonstrate how to capture the area-complexity of a Boolean function using the complexity of its Boolean derivatives. We evaluate the metric on circuits from MCNC benchmark suite and a sizeable collection of randomly generated circuits. We compare our metric with existing techniques based on literal-count and BDD properties. We show that the new area-complexity measure is accurate within 10% of the actual number of gates synthesized using ABC as opposed to at least 100% and 15% for the metrics based on literal-count and BDD properties respectively. We also show the robustness of our metric across three different gate-libraries.
Citations
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Proceedings ArticleDOI
14 Mar 2016
TL;DR: A resource-aware functional patch generation approach by gate count and wiring cost estimations, which considers the physical location of the patch and a set of nearby spare cells and produces the patch with minimal wiring cost instead of minimal size.
Abstract: Functional Engineering Change Order (ECO) is necessary for logic rectification at late design stages. Existing works mainly focus on identifying a minimal logic difference between the original netlist and the revised netlist, which is called a patch. The patch is then implemented by technology mapping using spare cells. However, there may be insufficient spare cells around the physical location of the patch, or the wires connecting spare cells are too long, thus causing timing violations and routing congestion. In this paper, we propose a resource-aware functional patch generation approach by gate count and wiring cost estimations. In particular, we estimate the number of spare cells required by a patch and define a cost of wire length on it, which considers the physical location of the patch and a set of nearby spare cells. As a result, the patch with minimal wiring cost instead of minimal size is produced. The experiments are conducted on nine industrial testcases. These testcases reflect real problems faced by designers, and the results show our method is promising.

10 citations

References
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Journal Article
TL;DR: Copyright (©) 1999–2012 R Foundation for Statistical Computing; permission is granted to make and distribute verbatim copies of this manual provided the copyright notice and permission notice are preserved on all copies.
Abstract: Copyright (©) 1999–2012 R Foundation for Statistical Computing. Permission is granted to make and distribute verbatim copies of this manual provided the copyright notice and this permission notice are preserved on all copies. Permission is granted to copy and distribute modified versions of this manual under the conditions for verbatim copying, provided that the entire resulting derived work is distributed under the terms of a permission notice identical to this one. Permission is granted to copy and distribute translations of this manual into another language, under the above conditions for modified versions, except that this permission notice may be stated in a translation approved by the R Core Team.

272,030 citations


"Measuring Area-Complexity Using Boo..." refers methods in this paper

  • ...We use R Statistical Computing Tool [13], to perform linear regression....

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Journal ArticleDOI
TL;DR: A basic part of the general synthesis problem is the design of a two-terminal network with given operating characteristics, and this work shall consider some aspects of this problem.
Abstract: THE theory of switching circuits may be divided into two major divisions, analysis and synthesis. The problem of analysis, determining the manner of operation of a given switching circuit, is comparatively simple. The inverse problem of finding a circuit satisfying certain given operating conditions, and in particular the best circuit is, in general, more difficult and more important from the practical standpoint. A basic part of the general synthesis problem is the design of a two-terminal network with given operating characteristics, and we shall consider some aspects of this problem.

774 citations


"Measuring Area-Complexity Using Boo..." refers background in this paper

  • ...The area-complexity of a circuit can be measured in terms of the number of inputs or literals or gates, etc. Characterizing logic functions and estimation of areacomplexity dates back to 1949 when Shannon [1] measured the area-complexity as the amount of switching activity in the circuit....

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  • ...We exploit this relationship and propose a metric for estimating the number of logic gates required by a function....

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Journal ArticleDOI

201 citations


"Measuring Area-Complexity Using Boo..." refers background in this paper

  • ...For a Boolean function F (x1, x2, ..., xn), the cofactor of F (Fa) w.r.to a literal a = xi or a = x̄i is defined as Fxi(x1, ..., xi, ..., xn) = F (x1, ..., 1, ..., xn) Fx̄i(x1, ..., xi, ..., xn) = F (x1, ..., 0, ..., xn) Fxi and Fx̄i are called the positive cofactor and the negative cofactor of F…...

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  • ...1 and 2 are called as the 1-fold and the 2-fold Boolean derivatives of F respectively....

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Journal ArticleDOI
TL;DR: The basic definitions of binary decision diagrams (BDDs) are reviewed and several applications of BDDs and their extensions are outlined and a number of articles and books are suggested for those who wish to pursue the topic in more depth.
Abstract: Decision diagrams (DDs) are the state-of-the-art data structure in VLSI CAD and have been successfully applied in many other fields. DDs are widely used and are also integrated in commercial tools. This special section comprises six contributed articles on various aspects of the theory and application of DDs. As preparation for these contributions, the present article reviews the basic definitions of binary decision diagrams (BDDs). We provide a brief overview and study theoretical and practical aspects. Basic properties of BDDs are discussed and manipulation algorithms are described. Extensions of BDDs are investigated and by this we give a deeper insight into the basic data structure. Finally we outline several applications of BDDs and their extensions and suggest a number of articles and books for those who wish to pursue the topic in more depth.

140 citations


"Measuring Area-Complexity Using Boo..." refers methods in this paper

  • ...With rising popularity of BDDs in the 1990’s, many metrics used the structural parameters of the BDDs, like the number of nodes, as an area-complexity measure [7], [8]....

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Journal ArticleDOI
TL;DR: The proposed area model is based on transforming the given, multi-output Boolean function description into an equivalent single-output function, and is empirical, and results demonstrating its feasibility and utility are presented.
Abstract: High-level power estimation, when given only a high-level design specification such as a functional or register-transfer level (RTL) description, requires high-level estimation of the circuit average activity and total capacitance. Considering that total capacitance is related to circuit area, this paper addresses the problem of computing the "area complexity" of multi-output combinational logic given only their functional description, i.e., Boolean equations, where area complexity refers to the number of gates required for an optimal multilevel implementation of the combinational logic. The proposed area model is based on transforming the multi-output Boolean function description into an equivalent single output function. The area model is empirical and results demonstrating its feasibility and utility are presented. Also, a methodology for converting the gate count estimates, obtained from the area model, into capacitance estimates is presented. High-level power estimates based on the total capacitance estimates and average activity estimates are also presented.

119 citations


"Measuring Area-Complexity Using Boo..." refers background in this paper

  • ...This can lead to overprediction of the number of gates as frequent application of logic synthesis algorithms often reduces the gate-count....

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